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H5TQ4G63AFR-RDC 数据表(PDF) 27 Page - Hynix Semiconductor |
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H5TQ4G63AFR-RDC 数据表(HTML) 27 Page - Hynix Semiconductor |
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27 / 35 page ![]() Rev. 1.0 / Apr. 2013 27 Standard Speed Bins DDR3L SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. DDR3-800 Speed Bins For specific Notes See "Speed Bin Table Notes" on page 33. Speed Bin DDR3-800E Unit Notes CL - nRCD - nRP 6-6-6 Parameter Symbol min max Internal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 — ns PRE command period tRP 15 — ns ACT to ACT or REF command period tRC 52.5 — ns ACT to PRE command period tRAS 37.5 9 * tREFI ns CL = 5 CWL = 5 tCK(AVG) 3.0 3.3 ns 1,2,3,4,12,13 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3 Supported CL Settings 5, 6 nCK 13 Supported CWL Settings 5 nCK |
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