J T A G

P R OB E S

F OR

S I GN U M

E M ULATO RS

T E CHNI CA L

S P E C IF IC A TION S

13

E M UL A T OR

S I DE

SW I TC H

P R OB E

S I DE

EMU0

EMU1

EMU0

nSYSRST

EMU1

FIGURE 33 The DIP switches SW1-4 on the CTI20 probe in default setting positions.

S W1

S W2

S W3

S W4

Default – EMU01 and EMU1

controlled in standard way

ON

OFF

ON

OFF

Emulator’s EMU0 connected

to CTI20 probes’s nSYSRST

OFF

ON

ON

OFF

Emulator’s EMU1 connected

to CTI20 probe’s nSYSRST

ON

OFF

OFF

ON

EMU0, EMU1 and nSYSRST

disconnected from target

(only weak pull-up resistors used)

OFF

OFF

OFF

OFF

TABLE 5 The allowed settings of the ADA-JET-CTI20 probe.

Note 1

Set the SW1-4 switches only when the emulator and the target are not powered!

Note 2

Do not set SW1-2 and SW3-4 pairs both ON. The setting will short the EMU0, EMU1

and nSYSRTS lines on the target.

Note 3

The nSYSRTS, EMU0 and EMU1 lines are bi-directional and are driven by an open-

collector gate in the emulator. EMU0 and EMU1 have 100K pull-ups to the PD pin on

the probe side, while nSYSRST has 220K pull-up to the PD pin.

Note 4

Certain JTAGjet driver packages may not easily allow configuring EMU0 and EMU1 as

nSYSRST. Therefore it is recommended to leave the DIP switch in its default position.

The software is unable determine the position of this switch automatically. When SW2 or

SW4 are ON, the software needs to be configured accordingly. Sample settings that allow

EMU0 to act as a CPU reset signal (nSYSRST) are shown in Figure 34.

FIGURE 34 Configuring the JTAGjet-eBinder driver to use

the EMU0 signal as the CPU reset signal (EmuDiag for the

JTAGjet-eBinder).

All future releases of the JTAGjet software will allow the user to redefine the EMU0 and EMU1 pins as CPU

reset pins.

SW1

SW2

SW3

SW4