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S12CPUV2 数据表(PDF) 1 Page - Freescale Semiconductor, Inc |
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S12CPUV2 数据表(HTML) 1 Page - Freescale Semiconductor, Inc |
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1 / 2 page  2 x SCI 3 x SPI 2 x CAN 2.0 A/B PWM 8-bit, 8 ch./16-bit, 4-ch. HCS12 CPU 16-Key Wake-Up IRQ Ports Vreg 5V to 2.5V Enhanced Capture Timer 16-bit, 8-ch. ATD0 10-bit, 8-ch. 12 KB RAM 256 KB Flash 4 KB EEPROM ATD1 10-bit, 8-ch. I2C 16-bit Microcontrollers MC9S12DG256 Overview Freescale Semiconductor’s HCS12 Family of microcontrollers (MCUs) is the next generation of the highly successful 68HC12 architecture. Using Freescale’s industry-leading 0.25 µs Flash, the MC9S12DG256 is part of a pin-compatible family that scales from 32 KB to 512 KB of Flash memory. The MC9S12DG256 provides an upward migration path from Freescale’s 68HC08, 68HC11 and 68HC12 architectures for applications that need larger memory, more peripherals and higher performance. Also, with the increasing number of CAN-based electronic control units (ECUs), its multiple network modules support this environment by enabling highly efficient communications between different network buses. Target Applications > Automotive applications > Industrial control Features Benefits High-Performance 16-bit HCS12 CPU Core > 25 MHz bus operation at 5V for 40 ns minimum instruction cycle time > Opcode compatible with the 68HC11 and 68HC12 > C-optimized architecture produces extremely compact code On-Chip Debug Interface > Dedicated serial debug interface > On-chip breakpoints > Real-time in-circuit emulation and debug without expensive and cumbersome box emulators > Read/write memory and registers while running at full speed Network Modules Integrated Third-Generation Flash Memory 4 KB Integrated EEPROM > Flexible protection scheme for protection against accidental program or erase > EEPROM can be programmed in 46 µs > Can erase 4 bytes at a time and program 2 bytes at a time for calibration, security, personality and diagnostic information > Two msCAN modules implementing the CAN 2.0 A/B protocol • Five receive buffers per module with FIFO storage scheme • Three transmit buffers per module with internal prioritization > Ability to link modules for higher buffer count > Programmable bit rate up to 1 Mbps > FIFO receive approach superior for event-driven networks > In-application reprogrammable > Self-timed, fast programming • Fast Flash page erase—20 ms (512 bytes) • Can program 16 bits in 20 µs while in burst mode > 5V Flash program/erase/read > Flash granularity—512 byte Flash erase/2 byte Flash program > Four independently programmable Flash arrays > Flexible block protection and security > Flexibility to change code in the field > Efficient end-of-line programming > Total program time for 256 KB code is less than 10 seconds > Reduces production programming cost through ultra-fast programming > No external high voltage or charge pump required > Virtual EEPROM implementation, Flash array usable for EE extension > Can erase one array while executing code from another |
类似零件编号 - S12CPUV2 |
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类似说明 - S12CPUV2 |
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