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MPC8349EVVALFB 数据表(PDF) 81 Page - Freescale Semiconductor, Inc |
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MPC8349EVVALFB 数据表(HTML) 81 Page - Freescale Semiconductor, Inc |
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81 / 87 page ![]() MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13 Freescale Semiconductor 81 System Design Information have a low ESR (equivalent series resistance) rating to ensure the quick response time. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors are 100–330 µF (AVX TPS tantalum or Sanyo OSCON). 21.4 Connection Recommendations To ensure reliable operation, connect unused inputs to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the MPC8349EA. 21.5 Output Buffer DC Impedance The MPC8349EA drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I2C). To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then the value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 43). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN are designed to be close to each other in value. Then, Z0 = (RP + RN) ÷ 2. Figure 43. Driver Impedance Measurement Two measurements give the value of this resistance and the strength of the driver current source. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V1 = Rsource × Isource. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value Rterm. The measured voltage is OVDD OGND RP RN Pad Data SW1 SW2 |
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