MCP4341T104ESLASHML datasheet(44/80 Pages) MICROCHIP

44 / 80 page

MCP434X/436X

DS22233A-page 44

6.1

SDI, SDO, SCK, and CS Operation

The operation of the four SPI interface pins are

discussed in this section. These pins are:

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

•CS (Chip Select)

The serial interface works on either 8-bit or 16-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

6.1.1

SERIAL DATA IN (SDI)

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the rising

edge of the SCK signal.

6.1.2

SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Once the CS pin is forced to the active level (VIL or

VIHH), the SDO pin will be driven. The state of the SDO

pin is determined by the serial bit’s position in the

command, the command selected, and if there is a

command error state (CMDERR).

6.1.3

SERIAL CLOCK (SCK)

(SPI FREQUENCY OF OPERATION)

The SPI interface is specified to operate up to 10 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

TABLE 6-1:

SCK FREQUENCY

6.1.4

THE CS SIGNAL

The Chip Select (CS) signal is used to select the device

and frame a command sequence. To start a command,

or sequence of commands, the CS signal must

transition from the inactive state (VIH) to an active state

(VIL or VIHH).

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (VIL). To exit the

error condition, the user must take the CS pin to the VIH

level.

When the CS pin returns to the inactive state (VIH) the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (VIH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

The CS pin has an internal pull-up resistor. The resistor

is disabled when the voltage on the CS pin is at the VIL

level. This means that when the CS pin is not driven,

the internal pull-up resistor will pull this signal to the VIH

level. When the CS pin is driven low (VIL), the

resistance becomes very large to reduce the device

current consumption.

The high voltage capability of the CS pin allows High

Voltage commands. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

Memory Type Access

Command

Read

Write,

Increment,

Decrement

Non-Volatile

Memory

SDI, SDO

10 MHz

10 MHz (1, 2)

Volatile

Memory

SDI, SDO

10 MHz

Note 1:

Non-Volatile memory does not support the

Increment or Decrement command.

After a Write command, the internal write

cycle must complete before the next SPI

command is received.

This is the maximum clock frequency

without an external pull-up resistor.

Note:

There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

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