24LC512TISLASHP datasheet(13/36 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS21754M-page 13

24AA512/24LC512/24FC512

8.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

control byte is set to ‘

1’. There are three basic types of

read operations: current address read, random read

and sequential read.

8.1

Current Address Read

The 24XX512 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by ‘

1’. Therefore, if the previous read

access was to address ‘n’ (n is any legal address), the

next current address read operation would access data

from address n + 1.

Upon receipt of the control byte with R/W bit set to ‘

1’,

the 24XX512 issues an acknowledge and transmits the

8-bit data word. The master will not acknowledge the

transfer but does generate a Stop condition and the

24XX512 discontinues transmission (Figure 8-1).

FIGURE 8-1:

CURRENT ADDRESS

READ

8.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24XX512 as part of a write operation (R/W bit set to

‘

0’). After the word address is sent, the master

generates a Start condition following the acknowledge.

This terminates the write operation, but not before the

internal Address Pointer is set. Then, the master issues

the control byte again but with the R/W bit set to a one.

The 24XX512 will then issue an acknowledge and

transmit the 8-bit data word. The master will not

acknowledge the transfer but does generate a Stop

condition which causes the 24XX512 to discontinue

transmission (Figure 8-2). After a random Read

command, the internal address counter will point to the

address location following the one that was just read.

8.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX512 transmits

the first data byte, the master issues an acknowledge

as opposed to the Stop condition used in a random

read. This acknowledge directs the 24XX512 to

transmit the next sequentially addressed 8-bit word

(Figure 8-3). Following the final byte transmitted to the

master, the master will NOT generate an acknowledge,

but will generate a Stop condition. To provide

sequential reads, the 24XX512 contains an internal

Address Pointer which is incremented by one at the

completion of each operation. This Address Pointer

allows the entire memory contents to be serially read

during one operation. The internal Address Pointer will

automatically roll over from address FFFF to address

0000 if the master acknowledges the byte received

from the array address FFFF.

Bus Activity

Master

SDA Line

Bus Activity

Control

Byte

Data

00 AA A 1

Byte

21 0

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