EP3SL200 datasheet(53/341 Pages) ALTERA

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics

1–43

I/O Timing

Altera Corporation

Stratix III Device Handbook, Volume 2

1.2-V

HSTL

CLASS I

GCLK

0.904

0.906

1.473

-1.503 -1.682 -1.598 -1.620 -1.497 -1.674 -1.587 -1.665

-0.655

-0.645

1.473

-1.311 -1.418 -1.362 -1.630 -1.322 -1.428 -1.374 -1.666

GCLK

PLL

-0.884

-0.914

-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875

0.997

1.040

1.554

1.774

1.924

1.808

1.834

1.768

1.931

1.777

1.885

1.2-V

HSTL

CLASS II

GCLK

0.910

0.917

1.476

1.619

1.864

1.796

2.057

1.645

1.878

1.814

2.090

-0.661

-0.656

-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875

GCLK

PLL

-0.884

-0.914

-1.291 -1.412 -1.634 -1.580 -1.842 -1.428 -1.639 -1.588 -1.875

0.997

1.040

1.554

1.774

1.924

1.808

1.834

1.768

1.931

1.777

1.885

3.0-V PCI

GCLK

0.910

0.917

1.476

1.619

1.864

1.796

2.057

1.645

1.878

1.814

2.090

-0.661

-0.656

-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880

GCLK

PLL

-0.890

-0.925

1.473

1.620

1.867

1.799

2.060

1.644

1.883

1.819

2.095

1.003

1.051

-1.288 -1.413 -1.637 -1.583 -1.845 -1.427 -1.644 -1.593 -1.880

3.0-V

PCI-X

GCLK

0.904

0.906

1.557

1.773

1.921

1.805

1.831

1.769

1.926

1.772

1.880

-0.655

-0.645

1.473

1.620

1.867

1.799

2.060

1.644

1.883

1.819

2.095

GCLK

PLL

-0.890

-0.925

1.482

1.633

1.882

1.814

2.075

1.653

1.893

1.829

2.105

1.003

1.051

-1.297 -1.426 -1.652 -1.598 -1.860 -1.436 -1.654 -1.603 -1.890

Table 1–42. EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3)

I/O

Standard

Clock

Fast Model

C4L

I4L

Units

Industrial

Commercial

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

1.1 V

CCL=

0.9 V

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