Pin Information

Page 21

Configuration Devices for SRAM-Based LUT Devices

January 2012

Altera Corporation

Pin Information

Table 20 lists the pin functions of the EPC1, EPC2, and EPC1441 devices during device

configuration.

Configuration (EPC) Devices Datasheet.

Configuration (EPCS) Devices Datasheet.

Table 20. EPC1, EPC2, and EPC1441 Device Pin Functions During Configuration (Part 1 of 3)

Pin Name

Pin Number

Pin Type

Description

8-Pin

PDIP (1)

20-Pin

PLCC

32-Pin

TQFP (2)

DATA

12

31

Output

Serial data output. The DATA pin connects to the DATA0 pin

of the FPGA. DATA is latched into the FPGA on the rising

edge of DCLK.

The DATA pin is tri-stated before configuration and when

the nCS pin is high. After configuration, the EPC2 device

drives DATA high, while the EPC1 and EPC1441 device

tri-state DATA.

DCLK

2

4

2

Bidirectional

Clock output when configuring with a single configuration

device or when the configuration device is the first

(master) device in a chain. Clock input for the next (slave)

configuration devices in a chain. The DCLK pin connects to

the DCLK pin of the FPGA.

Rising edges on DCLK increment the internal address

counter and present the next bit of data on the DATA pin.

The counter is incremented only if the OE input is held

high, the nCS input is held low, and all configuration data

has not been transferred to the target device.

After configuration or when OE is low, the EPC1, EPC2 and

EPC1441 device drive DCLK low.

OE

387

Open-drain

bidirectional

Output enable (active high) and reset (active low). The OE

pin connects to the nSTATUS pin of the FPGA.

A low logic level resets the address counter. A high logic

level enables DATA and the address counter to count. If this

pin is low (reset) during configuration, the internal

oscillator becomes inactive and DCLK drives low. For more

information, refer to “Error Detection Circuitry” on page 9.

The OE pin has an internal programmable 1-k

 resistor in

EPC2 devices. If internal pull-up resistors are used, do not

use external pull-up resistors on these pins. You can

disable the internal pull-up resistors through the Disable

nCS

and OE pull-ups on configuration device option.