8

0364J–PLD–7/05

ATF16V8B/BQ/BQL

6.

Electronic Signature Word

There are 64 bits of programmable memory that are always available to the user, even if the

device is secured. These bits can be used for user-specific data.

7.

Programming/Erasing

Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro-

gramming Hardware and Software Support for information on software/programming.

8.

Input and I/O Pull-ups

All ATF16V8B family members have internal input and I/O pull-up resistors. Therefore, when-

ever inputs or I/Os are not being driven externally, they will float to V

logic array inputs are at known states. These are relatively weak active pull-ups that can easily

be overdriven by TTL-compatible drivers (see input and I/O diagrams below).

Figure 8-1.

Input Diagram

Figure 8-2.

I/O Diagram

9.

Functional Logic Diagram Description

The Logic Option and Functional Diagrams describe the ATF16V8B architecture. Eight config-

urable macrocells can be configured as a registered output, combinatorial I/O, combinatorial

output, or dedicated input.

The ATF16V8B can be configured in one of three different modes. Each mode makes the

ATF16V8B look like a different device. Most PLD compilers can choose the right mode automat-

ically. The user can also force the selection by supplying the compiler with a mode selection.

The determining factors would be the usage of register versus combinatorial outputs and dedi-

cated outputs versus outputs with output enable control.

The ATF16V8B universal architecture can be programmed to emulate many 20-pin PAL

devices. These architectural subsets can be found in each of the configuration modes described