COM0A1 datasheet(21/294 Pages) ATMEL

21 / 294 page

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

Figure 3-2.

Data Memory Map

3.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk

CPU cycles as described in Figure 3-3.

Figure 3-3.

On-chip Data SRAM Access Cycles

3.3

EEPROM Data Memory

The Atmel® AVR® contains EEPROM memory (see “E2 size” in Table 3-1 on page 19). It is

organized as a separate data space, in which single bytes can be read and written. The

EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The

access between the EEPROM and the CPU is described in the following, specifying the

EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control

Section 22. “Memory Programming” on page 236 contains a detailed description on EEPROM

programming in SPI or Parallel Programming mode.

32 Registers

64 I/O Registers

Internal SRAM

(ISRAM size)

0x0000 - 0x001F

0x0020 - 0x005F

ISRAM end

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.

ISRAM start

clk

Data

Address

Address valid

Compute Address

CPU

Memory Access Instruction

Next Instruction

COM0A1 数据表(PDF) 21 Page - ATMEL Corporation

COM0A1 数据表(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载