TLV5626

2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS236A –JUNE 1999 – REVISED JUNE 2000

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating conditions (unless otherwise noted)

(Continued)

reference pin configured as output (REF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Vref(OUTL)

Low reference voltage

1.003

1.024

1.045

V

Vref(OUTH)

High reference voltage

VDD > 4.75 V

2.027

2.048

2.069

V

Iref(source)

Output source current

1

mA

Iref(sink)

Output sink current

–1

mA

Load capacitance

100

pF

PSRR

Power supply rejection ratio

–65

dB

reference pin configured as input (REF)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VI

Input voltage

0

VDD–1.5

V

RI

Input resistance

10

M

Ω

CI

Input capacitance

5

pF

Reference input bandwidth

REF=0 2V

+1 024Vdc

Fast

1.3

MHz

Reference input bandwidth

REF = 0.2 Vpp + 1.024 V dc

Slow

525

kHz

Reference feedthrough

REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)

–80

dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = VDD

1

µA

IIL

Low-level digital input current

VI = 0 V

–1

µA

Ci

Input capacitance

8

pF

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

t (FS)

Output settling time full scale

RL = 10 kΩ,CL = 100 pF,

Fast

0.8

2.4

µs

ts(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow

2.8

5.5

µs

t (CC)

Output settling time code to code

RL = 10 kΩ,CL = 100 pF,

Fast

0.4

1.2

µs

ts(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow

0.8

1.6

µs

SR

Slew rate

RL = 10 kΩ,CL = 100 pF,

Fast

12

V/

µs

SR

Slew rate

L

,

L

,

See Note 13

Slow

1.8

V/

µs

Glitch energy

DIN = 0 to 1,

fCLK = 100 kHz,

CS = VDD

5

nV–S

SNR

Signal-to-noise ratio

53

57

S/(N+D)

Signal-to-noise + distortion

fs = 480 kSPS, fout = 1 kHz,

48

47

dB

THD

Total harmonic distortion

s

,

out

,

RL = 10 kΩ,CL = 100 pF

–50

–48

dB

SFDR

Spurious free dynamic range

50

62

NOTES: 11. Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFD0 or 0xFD0 to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within

± 0.5 LSB of the final measured value for a digital input code change

of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.