AD5245

Rev. B | Page 14 of 20

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

A

W

B

Figure 37. Potentiometer Mode Configuration

If ignoring the effect of the wiper resistance for approximation,

then connecting the A terminal to 5 V and the B terminal to

ground produces an output voltage at the wiper-to-B starting at

0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal A and B divided by the 256

positions of the potentiometer divider. The general equation

valid input voltage applied to Terminals A and B is

B

A

W

V

D

V

D

D

V

256

256

256

)

(

−

+

=

(3)

A more accurate calculation, which includes the effect of wiper

B

AB

WA

A

AB

WB

W

V

R

D

R

V

R

D

R

D

V

)

(

)

(

)

(

+

=

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

values. Therefore, the temperature drift reduces to 15 ppm/°C.

ESD PROTECTION

All digital inputs are protected with a series of input resistors and

parallel Zener ESD structures, shown in Figure 38 and Figure 39.

This applies to the digital input pins SDA, SCL, and AD0.

LOGIC

340Ω

GND

Figure 38. ESD Protection of Digital Pins

A, B, W

GND

Figure 39. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

conditions for proper 3-terminal digital potentiometer

operation. Supply signals present on Terminals A, B, and W that

diodes (see Figure 40).

GND

A

W

B

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

at Terminals A, B, and W (see Figure 40), it is important to

A, B, and W; otherwise, the diode is forward biased such that

user’s circuit. The ideal power-up sequence is in the following

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ compact, minimum lead length

layout design. The leads to the inputs should be as direct as

possible with a minimum conductor length. Ground paths

should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies

with quality capacitors for optimum stability. Supply leads to

the device should be bypassed with disk or chip ceramic

capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum

or electrolytic capacitors should also be applied at the supplies

to minimize any transient disturbance and low frequency ripple

(see Figure 41). Note that the digital ground should also be

joined remotely to the analog ground at one point to minimize

the ground bounce.

GND

C3

10µF

C1

0.1µF

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+

Figure 41. Power Supply Bypassing