ADCMP572/ADCMP573

Rev. A | Page 12 of 16

TYPICAL APPLICATION CIRCUITS

Q

3.3V

50

Ω

50

Ω

ADCMP572

Q

LATCH

INPUTS

LATCH

INPUTS

Figure 21. Zero-Crossing Detector with 3.3 V CML Outputs

Q

50

Ω

50

Ω

Q

5V

75

Ω

50

Ω

50

Ω

100

Ω

100

Ω

ADCMP572

Figure 25. Interfacing 3.3 V CML to a 50 Ω

Ground Terminated Instrument

LATCH

INPUTS

ADCMP572

Figure 22. LVDS to 50 Ω Back Terminated RSPECL Receiver

50

Ω

50

Ω

+

–

Q

Q

LATCH

ADCMP572

50Ω

1.35kΩ

50Ω

Figure 26. Disabling the ADCMP572 Latch Feature

INPUTS

GND = –1V

2.5V/3.3V

ADCMP572

Figure 23. Comparator with ±1 V Input Range and

2.5 V or 3.3 V CML Outputs

50

Ω

50

Ω

Q

Q

500

Ω

ADCMP573

50

Ω

50

Ω

Figure 27. Disabling the ADCMP573 Latch Feature

LATCH

INPUTS

3.3V/5.2V

ADCMP572

Figure 24. Comparator with 0 V to 3 V Input Range and

3.3 V or 5.2 V Positive CML Outputs

HYS

ADCMP572

50

Ω

50

Ω

0

Ω TO 5kΩ

Figure 28. Adding Hysteresis Using the HYS Control Pin