ADC0804LCWM datasheet(19/48 Pages) TI

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SNOSBI1B – NOVEMBER 2009 – REVISED FEBRUARY 2013

(1)

CS shown twice for clarity.

(2)

SAR = Successive Approximation Register.

Figure 48. Block Diagram

After the “1” is clocked through the 8-bit shift register (which completes the SAR search) it appears as the input

to the D-type latch, LATCH 1. As soon as this “1” is output from the shift register, the AND gate, G2, causes the

new digital word to transfer to the TRI-STATE output latches. When LATCH 1 is subsequently enabled, the Q

output makes a high-to-low transition which causes the INTR F/F to set. An inverting buffer then supplies the

INTR input signal.

Note that this SET control of the INTR F/F remains low for 8 of the external clock periods (as the internal clocks

run at 1/8 of the frequency of the external clock). If the data output is continuously enabled (CS and RD both

held low), the INTR output will still signal the end of conversion (by a high-to-low transition), because the SET

input can control the Q output of the INTR F/F even though the RESET input is constantly at a M "1M " level in

this operating mode. This INTR output will therefore stay low for the duration of the SET signal, which is 8

periods of the external clock frequency (assuming the A/D is not started during this interval).

When operating in the free-running or continuous conversion mode (INTR pin tied to WR and CS wired low – see

Continuous Conversions), the START F/F is SET by the high-to-low transition of the INTR signal. This resets the

SHIFT REGISTER which causes the input to the D-type latch, LATCH 1, to go low. As the latch enable input is

still present, the Q output will go high, which then allows the INTR F/F to be RESET. This reduces the width of

the resulting INTR output pulse to only a few propagation delays (approximately 300 ns).

When data is to be read, the combination of both CS and RD being low will cause the INTR F/F to be reset and

the TRI-STATE output latches will be enabled to provide the 8-bit digital outputs.

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