AD5160

Rev. B | Page 15 of 1

6

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at

wiper-to-B and wiper-to-A proportional to the input voltage at

positive, voltage across A to B, W to A, and W to B can be at

either polarity.

If ignoring the effect of the wiper resistance for approximation,

connecting the A terminal to 5 V and the B terminal to ground

produces an output voltage at the wiper-to-B starting at 0 V up

to 1 LSB less than 5 V. Each LSB of voltage is equal to the

voltage applied across Terminal A and Terminal B divided by

the 256 positions of the potentiometer divider. The general

ground for any valid input voltage applied to Terminal A and

Terminal B is

B

A

W

V

V

D

V

256

256

)

(

+

=

D

D

256 −

(3)

For a more accurate calculation, which includes the effect of

B

WA

A

WB

W

V

D

R

V

D

R

D

V

256

)

(

256

)

(

)

(

+

=

(4)

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent mainly on

absolute values. Therefore, the temperature drift reduces to

15 ppm/°C.

SPI-COMPATIBLE 3-WIRE SERIAL BUS

The AD5160 contains a 3-wire SPI-compatible digital interface

(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB

first. The format of the word is shown in

.

Table 6

The positive-edge sensitive CLK input requires clean transitions

to avoid clocking incorrect data into the serial input register.

Standard logic families work well. If mechanical switches are

used for product evaluation, they should be debounced by a

flip-flop or other suitable means. When CS is low, the clock

loads data into the serial register on each positive clock edge

(see

).

Figure 37

The data setup and data hold times in the specification table

determine the valid timing requirements. The AD5160 uses an

8-bit serial input data register word that is transferred to the

internal RDAC register when the CS line returns to logic high.

Extra MSB bits are ignored.

ESD PROTECTION

All digital inputs are protected with a series input resistor and

parallel Zener ESD structures are shown in Figure 40 and

Figure 41. This applies to SDI, CLK, and CS, which are the

digital input pins.

LOGIC

340Ω

GND

Figure 40. ESD Protection of Digital Pins

A,B,W

GND

Figure 41. ESD Protection of Resistor Terminals

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance

before applying any voltage to the A, B, and W terminals;

unintentionally and may affect the rest of the user’s circuit. The

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length

layout design. Keep the leads to the inputs as direct as possible

with a minimum conductor length. Ground paths should have

low resistance and low inductance.

Similarly, it is also a good practice to bypass the power supplies

with quality capacitors for optimum stability. Bypass supply

leads to the device with disc or chip ceramic capacitors of

0.01 μF to 0.1 μF. To minimize any transient disturbance and

low frequency ripple, apply low ESR 1 μF to 10 μF tantalum or

electrolytic capacitors at the supplies (see Figure 42). To

minimize the ground bounce, join the digital ground remotely

to the analog ground at a single point.

AD5160

C1

C3

GND

10

μF

0.1

μF

+

Figure 42. Power Supply Bypassing