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AD5290YRMZ10-R7 数据表(PDF) 10 Page - Analog Devices |
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AD5290YRMZ10-R7 数据表(HTML) 10 Page - Analog Devices |
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10 / 20 page ![]() AD5290 Data Sheet Rev. C | Page 10 of 20 PIN CONFIGURATION AND DESCRIPTIONS A 1 B 2 VSS 3 GND 4 CS 5 W 10 VDD 9 SDO 8 SDI 7 CLK 6 AD5290 TOP VIEW (Not to Scale) Figure 4. AD5290 Pin Configuration Table 6. AD5290 Pin Function Descriptions Pin No. Mnemonic Description 1 A A Terminal. VSS ≤ VA ≤ VDD. 2 B B Terminal. VSS ≤ VB ≤ VDD. 3 VSS Negative Supply. Connect to 0 V for single-supply applications. 4 GND Digital Ground. 5 CS Chip Select Input; Active Low. When CS returns high, data is loaded into the wiper register. 6 CLK Serial Clock Input. Positive edge triggered. 7 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. 8 SDO Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor. It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages. 9 VDD Positive Power Supply. 10 W W Terminal. VSS ≤ VW ≤ VDD. |
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