MPC8247VRTMFA datasheet(4/61 Pages) FREESCALE

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MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

Overview

— Floating-point unit (FPU) supports floating-point arithmetic

— Support for cache locking

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Low-power consumption

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Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

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Separate PLLs for G2_LE core and for the communications processor module (CPM)

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,

5.5:1, 6:1, 7:1, 8:1

— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1

ratios

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64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs—up to two external masters

— Supports single transfers and burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

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60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

– PCI-to-60x address remapping

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System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

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Eight bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other

user-definable peripherals

— Byte write enables

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x)

— Dedicated interface logic for SDRAM

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Disable CPU mode

MPC8247VRTMFA 数据表(PDF) 4 Page - Freescale Semiconductor, Inc

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