Data Sheet

ADN8831

Rev. A | Page 13 of 20

TEMPERATURE LOCK INDICATOR

The TMPGD (Pin 11) outputs a logic high when the OUT1 (Pin 4)

voltage reaches the IN2P (Pin 5) temperature setpoint (TEMPSET)

voltage. The TMPGD has a detection range of ±25 mV and a

10 mV typical hysteresis. This allows direct interfacing either to

the microcontrollers or to the supervisory circuitry.

SOFT START ON POWER-UP

The ADN8831 can be programmed to ramp up for a specified

time after the power supply is turned on or after the SD pin is

deasserted. This feature, called soft start, is useful for gradually

increasing the duty cycle of the PWM amplifier. The soft start

time is set with a single capacitor connected from SS (Pin 14) to

ground. The capacitor value is calculated by the following

equation:

SS

SS

C

×

=

τ

150

where:

SHUTDOWN MODE

The shutdown mode sets the ADN8831 into an ultralow current

state. The current draw in shutdown mode is typically 8 µA.

The shutdown input, SD (Pin 16), is active low. To shut down

the device, drive SD to logic low. Once a logic high is applied,

the ADN8331 is reactivated after the time delay set by the soft

start circuitry. Refer to the Soft Start on Power-Up section for

more details.

STANDBY MODE

The ADN8831 has a standby mode that deactivates a MOSFET

driver stage. The current draw for the ADN8831 in standby

mode is less than 2 mA. The standby input SS/SB (Pin 14) is

active low. After applying a logic high, the ADN8331 reactivates

following the delay. In standby mode, only SYNCO (Pin 15) has

a clock output. All the other function blocks are powered off.

TEC VOLTAGE/CURRENT MONITOR

The TEC real time voltage and current are detectable at VTEC

(Pin 30) and ITEC (Pin 29), respectively.

Voltage Monitor

VTEC (Pin 30) is an analog voltage output pin with a voltage

proportional to the actual voltage across the TEC. A center

VTEC voltage of 1.25 V corresponds to 0 V across a TEC. The

output voltage is calculated using the following equation:

)

(

25

.

0

V

25

.

1

SFB

LFB

VTEC

V

V

V

−

×

+

=

Current Monitor

ITEC (Pin 29) is an analog voltage output pin with a voltage

proportional to the actual current through the TEC. A center

ITEC voltage of 1.25 V corresponds to 0 A through the TEC.

The output voltage is calculated using the following equation:

)

(

25

V

25

.

1

CS

LFB

ITEC

V

V

V

−

×

+

=

The equivalent TEC current is calculated using the following

equation:

SENSE

ITEC

TEC

R

V

I

×

−

=

25

V

25

.

1

MAXIMUM TEC VOLTAGE LIMIT

The maximum TEC voltage is set by applying a voltage at

VLIM (Pin 31) to protect the TEC. This voltage can be set with

a resistor divider or a DAC. The voltage limiter operates in

bidirectional TEC voltage, and cooling and heating voltage.

Using a DAC

Both the cooling and heating voltage limits are set at the same

levels when a voltage source directly drives VLIM (Pin 31).

The maximum TEC voltage is calculated using the following

equation:

VLIM

MAX

TEC

V

V

×

= 5

)

(

where:

Using a Resistor Divider

Separate voltage limits are set using a resistor divider. The

internal current sink circuitry connected to VLIM (Pin 31) draws

a current when the ADN8831 drives the TEC in a heating

direction, which lowers the voltage at VLIM (Pin 31). The

current sink is not active when the TEC is driven in a cooling

direction; therefore, the TEC heating voltage limit is always

lower than the cooling voltage limit.

ADN8831

VLIM

VLIM

FREQ

Figure 16. Using a Resistor Divider