ADP5589ACBZ-02-R7 datasheet(18/52 Pages) AD

18 / 52 page

ADP5589

Data Sheet

Rev. B | Page 18 of 52

RESET_PULSE_WIDTH[1:0]

RESET_TRIGGER_TIME[2:0]

RESET1_EVENT_A[7:0]

RESET1_EVENT_B[7:0]

RESET1_EVENT_C[7:0]

KEY

SCAN

CONTROL

RST_PASSTHRU_EN

RST

(R4)

RESET1

GPI

SCAN

CONTROL

LOGIC

BLOCK

CONTROL

RESET2_EVENT_A[7:0]

RESET2_EVENT_B[7:0]

(C4)

RESET2

RESET1_

INITIATE

RESET2_

INITIATE

RESET

GEN 2

RESET

GEN 1

Figure 25. Reset Blocks

The RESET1 signal uses I/O Pin R4 as its output. A pass-

through mode allows the main RST pin to be output on the

R4 pin also.

The RESET2 signal uses I/O Pin C4 as its output.

The reset generation signals are useful in situations where the

system processor has locked up and the system is unresponsive

to input events. The user can press one of the reset event combina-

tions and initiate a system-wide reset. This alleviates the need

for removing the battery from the system and performing a

hard reset.

It is not recommended to use the immediate trigger time (see

the details of the RESET_CFG Register, 0x3D, in Table 69)

because this setting may cause false triggering.

INTERRUPTS

The INT pin can be asserted low if any of the internal interrupt

sources is active. The user can select which internal interrupts

interact with the external interrupt pin in register INT_EN

(Address 0x4E, Bits[7:0]) (refer to Table 86). allows the user to

choose whether the external interrupt pin remains asserted, or

deasserts for 50 µs, then reasserts, in the case that there are

multiple internal interrupts asserted, and one is cleared (refer

to Table 85).

EVENT_INT

EVENT_IEN

INT DRIVE

INT

INT_CFG

GPI_INT

GPI_IEN

LOGIC1_INT

LOGIC2_INT

LOGIC1_IEN

LOGIC2_IEN

OVRFLOW_INT

OVRFLOW_IEN

LOCK_INT

LOCK_IEN

Figure 26. Asserting INT Low

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