AS82527 datasheet(21/58 Pages) INNOVASIC

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IA82527

Data Sheet

CAN Serial Communications Controller

December 20, 2012

IA211080504-07

http://www.innovasic.com

Customer Support:

Page 21 of 58

(888) 824-4184

Table 3. Pin/Signal Descriptions (Continued)

Signal

Description

Name

PLCC

PQFP

p2.0

port 2, bit N (N = 7–0). Input/Output. Port 2 bits p2.7–

p2.0, can be individually programmed as inputs or

outputs. Programming is accomplished by writing to

the P2CONF Register (AFH). The 8 bits of the

P2CONF Register, P2CONF7–P2CONF0, correspond

directly to pins p2.7–p2.0. Writing a 0 to a bit in the

P2CONF Register causes the corresponding pin to be

configured as a high-impedance input. Writing a 1 to a

bit in the P2CONF Register causes the corresponding

pin to be configured as a push-pull output. All Port 2

pins have weak pull-ups until the port is configured by

writing to the P2CONF Register. The default value of

the P1CONF Register following a reset is 00H.

Data is read from Port 2 via the P2IN Register (CFH).

A logic 0 for any bit in this register means that a logic 0

was read from the corresponding pin; a logic 1 for any

bit means that a logic 1 was read from the

corresponding pin. The default value of the P2IN

Data is written to Port 2 via the P2OUT Register

(EFH). Writing a logic 0 to any bit in this register

means that a logic 0 is written to the corresponding

pin; writing a logic 1 to any bit means that a logic 1 is

written to the corresponding pin. The default value of

the P2OUT Register following a reset is 00H.

Two bits of Port 2 (P2.7 and P2.6) have alternate

functions based on CPU interface mode.

See Section 4.1.3 I/O Ports.

p2.1

p2.2

p2.3

p2.4

p2.5

p2.6

int_n/p2.6

p2.7

wrh_n/p2.7

rd_n

rd_n/e

read. Input. Active Low. Mode 0 and Mode 1. When

rd_n is asserted (low), it causes the IA82527 to drive

the data from the location being read onto the data

bus.

ready

ready/miso

ready. Output (open drain). Active High. Mode 0 and

Mode 1. When ready is asserted (high), it signals the

completion of a bus cycle. The ready output is

provided to force system CPU wait states as required.

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