Operation description

VIPER37

28/35

Doc ID 022218 Rev 1

Figure 30.

FB pin configuration 1

Figure 31.

FB pin configuration 2

8.11

Burst mode operation at no load or very light load

When the load decreases, the feedback loop reacts by lowering the feedback pin voltage. If

be switched on. After the MOSFET stops, as a result of the feedback reaction to the energy

reported in

Table 8 and Figure 32 shows this behavior. Depending on the output load, the

power alternates between periods of time in which the Power MOSFET is switching and is

enabled, with periods of time when the Power MOSFET is not switching; this working mode

is called burst mode. The power delivered to the output during switching periods exceeds

the load power demands; the excess of power is balanced from the non-switching period

where no power is processed. The advantage of burst mode operation is an average

switching frequency much lower then the normal operation working frequency, up to a few

hundred hertz, minimizing all frequency related losses. During burst mode the drain current

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

+

-

PWM

+

-

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

+

-

PWM

BURST

To disable logic

+

-

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES