DOC7707 datasheet(45/307 Pages) ETC1

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7707F–AVR–11/10

AT90USB82/162

independent of sleep mode. Refer to “Analog Comparator” on page 223 for details on how to

configure the Analog Comparator.

8.7.2

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned off. If

the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep

modes, and hence, always consume power. In the deeper sleep modes, this will contribute sig-

nificantly to the total current consumption. Refer to “Brown-out Detection” on page 49 for details

on how to configure the Brown-out Detector.

8.7.3

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, or the

Analog Comparator. If these modules are disabled as described in the sections above, the inter-

nal voltage reference will be disabled and it will not be consuming power. When turned on again,

the user must allow the reference to start up before the output is used. If the reference is kept on

in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on

page 52 for details on the start-up time.

8.7.4

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Interrupts” on page 63 for details on how to configure the Watchdog Timer.

8.7.5

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important is then to ensure that no pins drive resistive loads. In sleep modes where the I/O

clock (clk

I/O) is stopped, the input buffers of the device will be disabled. This ensures that no

power is consumed by the input logic when not needed. In some cases, the input logic is needed

for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input

Enable and Sleep Modes” on page 71 for details on which pins are enabled. If the input buffer is

enabled and the input signal is left floating or have an analog signal level close to V

CC/2, the

input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V

CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1). Refer to

“Digital Input Disable Register 1 – DIDR1” on page 224 for details.

8.7.6

On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode,

the main clock source is enabled, and hence, always consumes power. In the deeper sleep

modes, this will contribute significantly to the total current consumption.

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