ADA4817-2ACPZ-R2 datasheet(16/28 Pages) AD

16 / 28 page

ADA4817-1/ADA4817-2

Data Sheet

Rev. B | Page 16 of 28

Table 8. Power-Down Voltage Control

PD Pin

±5 V

+3 V, −2 V

Not active

>4 V

>2 V

Active

<2 V

<0 V

CAPACITIVE FEEDBACK

Due to package variations and pin-to-pin parasitics between the

single and the dual models, the ADA4817-2 has a little more

peaking then the ADA4817-1, especially at a gain of 2. The best

way to tame the peaking is to place a feedback capacitor across

the feedback resistor. Figure 46 shows the small signal frequency

response of the ADA4817-2 at a gain of 2 vs. CF. At first, no CF

was used to show the peaking, but then two other values of

0.5 pF and 1 pF were used to show how to reduce the peaking or

even eliminate it. As shown in Figure 46, if the power consumption

is a factor in the system, then using a larger feedback capacitor

is acceptable as long as a feedback capacitor is used across it to

control the peaking. However, if power consumption is not an

issue, then a lower value feedback resistor, such as 200 Ω, would

not require any additional feedback capacitance to maintain

flatness and lower peaking.

–3

–6

–9

10M

100M

10G

FREQUENCY (Hz)

RF = 348Ω

G = 2

VS = 10V

VOUT = 100mV p-p

RL = 100Ω

CF = 1pF

CF = 0.5pF

NO CF

Figure 46. Small Signal Frequency Response vs. Feedback Capacitor

(ADA4817-2)

HIGHER FREQUENCY ATTENUATION

There is another package variation problem between the SOIC

and the LFCSP package. The SOIC package shows approximately

1 dB to 1.5 dB of additional peaking at a gain of 1. This is due to

the parasitic in the SOIC package, which is not recommended

for very high frequency parts that exceed 1 GHz. A good approach

to reducing the peaking is to place a resistor, RS, in series with

the noninverting input. This creates a first-order pole formed

by RS and CIN, the common-mode input capacitance.

Figure 47 shows the higher frequency attenuation, which

reduces the peaking but also reduces the −3 dB bandwidth.

–9

–6

–3

10M

100M

10G

FREQUENCY (Hz)

RS = 100Ω

RS = 75Ω

RS = 50Ω

RS = 0Ω

RL = 100Ω

VS = ±5V

VOUT = 0.1V p-p

G = 1

Figure 47. Small Signal Frequency Response for Various RS (SOIC)

As shown in Figure 47, the peaking dropped by almost 2 dB

when RS = 0 Ω to RS = 100 Ω, and in return, the −3 dB bandwidth

dropped from 1 GHz to 700 MHz. To maintain the −3 dB

bandwidth and to reduce peaking, an RLC circuit is recommended

instead of RS, as shown in Figure 48.

10nH

120Ω

2pF

Figure 48. RLC Circuit

The R in parallel to the series LC forms a notch that can be

shaped to compensate for the peaking produced by the amplifier.

The result is a smooth 1 GHz −3 dB bandwidth, 250 MHz 0.1 dB

flatness, and less than 1 dB of peaking. This circuit should be

placed in the path of the noninverting input when the ADA4817-x

is used at a gain of 1. The RLC values may need tweaking

depending on the source impedance and the flatness and band-

width required. Figure 49 shows the frequency response after the

RLC circuit is in place.

–9

–6

–3

10M

100M

10G

FREQUENCY (Hz)

RLC

NO RLC

RL = 100Ω

VS = 10V

VOUT = 100mV p-p

G = 1

Figure 49. Frequency Response with RLC Circuit

ADA4817-2ACPZ-R2 数据表(PDF) 16 Page - Analog Devices

ADA4817-2ACPZ-R2 数据表(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表下载

链接网址

ADA4817-2ACPZ-R2 数据表(PDF) 16 Page - Analog Devices

ADA4817-2ACPZ-R2 数据表(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

数据表 下载

链接网址

数据表下载