AD6620AS datasheet(21/44 Pages) AD

21 / 44 page

AD6620

–21–

REV. A

The frequency of the SYNC_NCO pulses, and therefore the

accuracy of the synchronization, is determined by the value of

the NCO Sync Control Register at address 302 hex. The value

in this register is the SYNC_MASK and is interpreted as a

32-bit unsigned integer. This value controls the window around

the zero crossing of the NCO output sine wave in which the

NCO will output a SYNC_NCO pulse as a master. As a slave,

the value in this register will determine the number of MSBs

of the output sine wave that are synchronized with the master.

The Master and all slaves should use the same SYNC_MASK

word. This value should almost always be written as all 1s

(FFFFFFFF hex).

Effects of A/B Input on the NCO

If the AD6620 is run in Single Channel Real mode using frac-

tional rate input timing, the A/B input is used to enable the

NCO advancement. If the A/B line is held high longer than one

clock period, the NCO will advance for each rising edge of the

CLK while A/B is high. This is not normally the desired result

and thus A/B must be taken low after the first CLK period to

prevent anomalous NCO results. See additional details under

Fractional Rate Timing.

Phase Continuous Tuning with the AD6620

For synchronization purposes, the AD6620 NCO phase is reset

each time the NCO frequency register is either written to or

read from. This is accomplished by forcing an NCO Sync to

occur. Normally, phase-continuous tuning is required on the

transmit path to control spectral leakage. On the receive path

this in not usually a constraint. However, if phase-continuous

tuning is required with the AD6620, it can be accomplished by

configuring the AD6620 as a Sync Slave. In this manner, no

internal NCO sync is generated when the NCO frequency regis-

ter is written to. If multiple AD6620s are synchronized together,

a common external sync pulse can be used to lock each of the

receivers together at the appropriate point in time. It is also

possible to reconfigure the AD6620 after the NCO frequency

Master. The next time the NCO phase cycles through 0 degrees,

the NCO sync is exerted and the chip is again synchronized.

2ND ORDER CASCADED INTEGRATOR COMB FILTER

The CIC2 filter is a fixed-coefficient, decimating filter. It is

constructed as a second order CIC filter whose characteristics

are defined only by the decimation rate chosen. This filter can

process signals at the full rate of the input port (67 MHz) in all

input modes. The output rate of this stage is given by the equa-

tion below.

SAMP

CIC

The decimation ratio, MCIC2, is an unsigned integer that may

be between 1 and 16. This stage may be bypassed under certain

conditions by setting, MCIC2 equal to 1. For this to happen the

processing clock rate, fCLK must be two or more times the input

data rate, fSAMP. This is because the I and Q data is processed in

parallel within the CIC2 filter, and the I and Q output data is

then multiplexed through the same data pipe before it enters the

CIC5 filter.

The frequency response of the CIC2 filter is given by the follow-

ing equations.

CIC

()

–

=×









CIC

SAMP

CIC

()

sin

=×





























The scale factor, SCIC2 is a programmable unsigned integer

between 0 and 6. This serves as an attenuator that can reduce

the gain of the CIC2 in 6 dB increments. For the best dynamic

range, SCIC2 should be set to the smallest value possible (i.e.,

lowest attenuation) without creating an overflow condition.

This can be safely accomplished using the equation below, where

input_level is the largest fraction of full scale possible at the

input to this AD6620 (normally 1). The CIC2 scale factor is

not ignored when the CIC2 is bypassed.

MASKED

COUNT = 0?

SYNC

MASK

SYNC_NCO

NCO FREQ

AMPLITUDE

DITHER

COS

SIN

PHASE

DITHER

PHASE

OFFSET

PHASE

ACCUMULATOR

Figure 35. NCO Block Diagram

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