AD7392/AD7393

Rev. C | Page 12 of 20

THEORY OF OPERATION

The AD7392/AD7393 comprise a set of pin-compatible, 12-/10-

bit digital-to-analog converters (DACs). These single-supply

operation devices consume less than 100 μA of current while

operating from 2.7 V to 5.5 V power supplies, making them

ideal for battery-operated applications. They contain a voltage-

switched, 12-/10-bit, laser-trimmed DAC; rail-to-rail output op

amps; and a parallel input DAC register. The external reference

input has constant input resistance independent of the digital

code setting of the DAC. In addition, the reference input can be

consists of a CS write strobe and 12 data bits (D0 to D11) if

utilizing the AD7392 or 10 data bits (D0 to D9) if utilizing

the AD7393. An RS pin is available to reset the DAC register to

zero scale. This function is useful for power-on reset or system

failure recovery to a known state. Additional power savings are

accomplished by activating the SHDN pin, resulting in a 1.5 μA

maximum consumption sleep mode. While the supply voltage is

on, data is retained in the DAC register to reset the DAC output

when the part is taken out of shutdown (SHDN = 1).

DIGITAL-TO-ANALOG CONVERTERS

The voltage switched R-2R DAC generates an output voltage

that depends on the external reference voltage connected to

N

REF

OUT

D

V

V

2

×

=

(1)

where:

D

is the decimal data-word loaded into the DAC register.

N

is the number of bits of DAC resolution.

If the 10-bit AD7393 uses a 2.5 V reference, Equation 1

becomes

1024

5

.

2

D

V

OUT

×

=

(2)

1.25 V, for D = 512; full-scale voltage is 2.497 V. The LSB

step size is 2.5 × 1/1024 = 0.0024 V.

If the 12-bit AD7392 uses a 5.0 V reference, Equation 1

becomes

4096

D

V

V

REF

OUT

×

=

(3)

Using Equation 3, the AD7392 provides a nominal midscale volt-

The LSB step size is 5.0 × 1/4096 = 0.0012 V.

AMPLIFIER SECTION

The internal DACs output is buffered by a low power consump-

tion precision amplifier. The op amp has a 60 μs typical settling

time to 0.1% of full scale. There are slight differences in settling

time for negative slew signals vs. positive. Also, negative tran-

sition settling time to within the last 6 LSBs of 0 V has an extended

settling time. The rail-to-rail output stage of this amplifier has

been designed to provide precision performance while operating

near either power supply. Figure 27 shows an equivalent output

schematic of the rail-to-rail amplifier with its N-channel pull-

down FETs that pull an output load directly to GND. The

output sourcing current is provided by a P-channel, pull-up

device that can source current-to-GND terminated loads.

P-CH

N-CH

AGND

Figure 27. Equivalent Analog Output Circuit

The rail-to-rail output stage provides ±1 mA of output current.

The N-channel output pull-down MOSFET, shown in Figure 27,

has a 35 Ω on resistance that sets the sink current capability

near ground. In addition to resistive load driving capability, the

amplifier also has been carefully designed and characterized for

up to 100 pF capacitive load driving capability.

REFERENCE INPUT

The reference input terminal has a constant input resistance

independent of digital code, which results in reduced glitches

on the external reference voltage source. The high 2.5 MΩ input

resistance minimizes power dissipation within the AD7392/

simplest applications for saving an external reference voltage

supply. This connection results in a rail-to-rail voltage output

span maximizing the programmed range. The reference input

nonlinearity error performance are plotted in Figure 20 and

Figure 21. The ratiometric reference feature makes the AD7392/

AD7393 an ideal companion to ratiometric analog-to-digital

converters (ADCs) such as the AD7896.