LTC3530 datasheet(6/16 Pages) LINER

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LTC3530

3530fb

–

PWM

LOGIC

GATE

DRIVERS

AND

ANTICROSS

CONDUCTION

GND

OSC

SW A

SW1

VIN

SW2

SW D

ANTI-RING

ERROR

AMP

1.215V

REVERSE

AMP

SW B

SW C

VOUT

BURST

SHDN/SS

3530 BD

PWM

COMPARATORS

THERMAL

SHUTDOWN

SOFT-START

SHUTDOWN

1.215V

VREF

AUTOMATIC

BURST MODE

CONTROL

Gm = 1/60k

VREF

SLEEP

CIN

COUT

CBURST

CP1

RSS

CSS

RBURST

GND (Pin 5): Ground for the IC.

VOUT (Pin 6): Output of the Synchronous Rectiﬁer. A ﬁlter

capacitor is placed from VOUT to GND. A ceramic bypass

capacitor is recommended as close to the VOUT and GND

pins as possible.

VIN (Pin 7): Input Supply Voltage. Internal VCC for the IC.

A 10μF ceramic capacitor is recommended as close to the

VIN and GND pins as possible.

SHDN/SS (Pin 8): Combined Soft-Start and Shutdown.

Applied voltage <0.4V shuts down the IC. Tie to >1.4V to

enable the IC and >1.6V to ensure the error amp is not

clamped from soft-start. An R-C from the shutdown com-

mand signal to this pin will provide a soft-start function

by limiting the rise time of VC.

FB (Pin 9): Feedback Pin. Connect resistor divider tap here.

The output voltage can be adjusted from 1.8V to 5.25V.

The feedback reference is typically 1.215V.

VOUT = 1.215V • 1+

VC (Pin10): Error Amp Output. An R-C network is con-

nected from this pin to FB for loop compensation. Refer

to “Closing the Feedback Loop” section for component

selection guidelines. During Burst Mode operation, VC is

internally clamped.

Exposed Pad (Pin 11, DD Package Only): Ground. This

pin must be soldered to the PCB and electrically connected

to ground.

PIN FUNCTIONS

BLOCK DIAGRAM

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