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TMS320VC33 数据表(PDF) 43 Page - Texas Instruments |
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TMS320VC33 数据表(HTML) 43 Page - Texas Instruments |
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43 / 58 page  TMS320VC33 DIGITAL SIGNAL PROCESSOR SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004 43 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 interrupt response timing (continued) Reset or Interrupt Vector Read Fetch First Instruction of Service Routine H3 H1 INT3 --INT0 Pin (EDGEMODE = 0) INT3 --INT0 Flag ADDR Data Vector Address First Instruction Address INT3 --INT0 Pin (EDGEMODE = 1) tsu(INT-H1L)† tsu(INT-H1L)‡ tsu(INT-H1L)¶ tw(INT)§ th(H1L-INT) † Falling edge of H1 just detects INTx falling edge. ‡ Falling edge of H1 detects second INTx low, however flag clear takes precedence. § Nominal width ¶ Falling edge of H1 misses previous INTx low as INTx rises. Figure 29. INT3--INT0 Response Timing |
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