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TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

bootloader operation (continued)

Table 5. INT0 -- INT3 Sources

ACTIVE INTERRUPT

ADDRESS/SOURCE WHERE BOOT DATA IS

READ FROM

DATA FORMAT

INT0

0x001000

8, 16, or 32-bit width

INT1|

0x400000

8, 16, or 32-bit width

INT2

0xFFF000

8, 16, or 32-bit width

INT3

Serial Port

32-bit, external clock, and frame synch

When MCBL/MP = 1, the reset and interrupt vectors are hard-coded within the internal ROM. Since this is a

read-only device, these vectors cannot be modified. To enable user-defined interrupt routines, the internal

vectors contain fixed values that point to an internal section of SRAM beginning at 0x809FC1. Code execution

begins at these locations so it is important to place branch instructions (to the interrupt routine) at these locations

and not vectors.

The bootloader program requires a small stack space for calls and returns. Two SRAM locations at 0x809800

and 0x809801 are used for this stack. Data should not be boot loaded into these locations as this will corrupt

the bootloader program run-time stack. After the boot-load operation is complete, a program can reclaim these

locations. The simplest solution is to begin a program’s stack or uninitialized data section at 0x809800.

For additional detail on bootloader operation including the bootloader source code, see the TMS320C3x User’s

Guide (literature number SPRU031).

A bit I/O line or external logic can be used to safely disable the MCBL mode after bootloading is complete.

However, to ensure proper operation, the CPU should not be currently executing code or using external data

as the change takes place. In the following example, the XF0 pin is 3-state on reset, which allows the pullup

resistor to place the DSP in MCBL mode. The following code, placed at the beginning of an application then

causes the XF0 pin to become an active-logic-low output, changing the DSP mode to MP. The cache-enable

and RPTS instructions are used since they cause the LDI instruction to be executed multiple times even though

it has been fetched only once (before the mode change). In other words, the RPTS instruction acts as a

one-level-deep program cache for externally executed code. If the application code is to be executed from

internal RAM, no special provisions are needed.

LDI

8000h,ST

; Enable the cache

RPTS

; RPTS fetchs the following opcode 1 time

LDI

2h, IOF

; Drive MCBL/MP=0 for several cycles allowing

; the pipeline to clear

TMS320VC33

RPU

RESET

XF0

MCBL/MP

DVDD

RESET

Figure 10. Changing Bootload Select Pin

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