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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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AM3703 数据表(PDF) 2 Page - Texas Instruments |
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AM3703 数据表(HTML) 2 Page - Texas Instruments |
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2 / 280 page  AM3715, AM3703 SPRS616F – JUNE 2010 – REVISED AUGUST 2011 www.ti.com [CIR] Modes) Support for Non-Invasive Debug • Three Master/Slave High-Speed – ARM Cortex-A8 Memory Architecture: Inter-Integrated Circuit (I2C) Controllers • 32K-Byte Instruction Cache (4-Way – Camera Image Signal Processing (ISP) Set-Associative) • CCD and CMOS Imager Interface • 32K-Byte Data Cache (4-Way Set-Associative) • Memory Data Input • 256K-Byte L2 Cache • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface – 32K-Byte ROM • Glueless Interface to Common Video – 64K-Byte Shared SRAM Decoders – Endianess: • Resize Engine • ARM Instructions - Little Endian – Resize Images From 1/4x to 4x • ARM Data – Configurable – Separate Horizontal/Vertical Control • Removable Media Interfaces: – System Direct Memory Access (SDMA) – Three Multimedia Card (MMC)/ Secure Digital Controller (32 Logical Channels With (SD) With Secure Data I/O (SDIO) Configurable Priority) • Test Interfaces – Comprehensive Power, Reset, and Clock – IEEE-1149.1 (JTAG) Boundary-Scan Management Compatible • SmartReflexTM Technology – Embedded Trace Macro Interface (ETM) • Dynamic Voltage and Frequency Scaling – Serial Data Transport Interface (SDTI) (DVFS) • 12 32-bit General Purpose Timers – Sitara™ ARM® Cortex™-A8 Core • 2 32-bit Watchdog Timers • ARMv7 Architecture • 1 32-bit Secure Watchdog Timer – TrustZone® • 1 32-bit 32-kHz Sync Timer – Thumb®-2 • Up to 188 General-Purpose I/O (GPIO) Pins – MMU Enhancements (Multiplexed With Other Device Functions) • In-Order, Dual-Issue, Superscalar • 45-nm CMOS Technology Microprocessor Core • Package-On-Package (POP) Implementation for • NEON Multimedia Architecture Memory Stacking (Not Available in CUS • Over 2x Performance of ARMv6 SIMD Package) • Supports Both Integer and Floating Point • Packages: SIMD – 515-pin s-PBGA package (CBP Suffix), .5mm • Jazelle® RCT Execution Environment Ball Pitch (Top), .4mm Ball Pitch (Bottom) Architecture – 515-pin s-PBGA package (CBC • Dynamic Branch Prediction with Branch Suffix), .65mm Ball Pitch (Top), .5mm Ball Target Address Cache, Global History Pitch (Bottom) Buffer, and 8-Entry Return Stack – 423-pin s-PBGA package (CUS • Embedded Trace Macrocell (ETM) Suffix), .65mm Ball Pitch 2 AM3715, AM3703 Sitara ARM Microprocessors Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3715 AM3703 |
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