LP2998

GND

+

+

+

SD

SD

LP2998

AVIN

GND

+

+

+

SD

SD

LP2998

GND

+

+

+

SD

SD

LP2998

www.ti.com

SNVS521I – DECEMBER 2007 – REVISED APRIL 2013

Figure 19. Recommended SSTL-2 Implementation

If power dissipation or efficiency is a major concern then the LP2998 has the ability to operate on split power

rails (see Figure 20). The output stage (PVIN) can be operated on a lower rail such as 1.8V and the analog

circuitry (AVIN) can be connected to a higher rail such as 2.5V, 3.3V or 5V. This allows the internal power

continuous current is reduced because of the lower rail voltage, although it is adequate for all motherboard

SSTL-2 applications. Increasing the output capacitance can also help if periods of large load transients will be

encountered.

Figure 20. Lower Power Dissipation SSTL-2 Implementation

The third option for SSTL-2 applications in the situation that a 1.8V rail is not available and it is not desirable to

use 2.5V, is to connect the LP2998 power rail to 3.3V (see Figure 21). In this situation AVIN will be limited to

operation on the 3.3V or 5V rail as PVIN can never exceed AVIN. This configuration has the ability to provide the

maximum continuous output current at the downside of higher thermal dissipation. Care should be taken to

prevent the LP2998 from experiencing large current levels which cause the device to exceed the maximum

operating junction temperature. Because of this risk it is not recommended to supply the output stage with a

voltage higher than a nominal 3.3V rail.

Figure 21. SSTL-2 Implementation With Higher Voltage Rails

Copyright © 2007–2013, Texas Instruments Incorporated

Submit Documentation Feedback

13

Product Folder Links: LP2998