REV. B

AD7724

–4–

TIMING CHARACTERISTICS

1, 2

Parameter

(A Version)

Unit

Conditions/Comments

100

kHz min

Master Clock Frequency

15

MHz max

13 MHz for Specified Performance

14

ns max

MCLK to SCLK Delay

67

ns min

Master Clock Period

0.45

× t

MCLK

ns min

Master Clock Input High Time

0.45

ns min

Master Clock Input Low Time

15

ns min

Data Hold Time After SCLK Rising Edge

10

ns min

RESET Pulsewidth

10

ns min

RESET Low Time Before MCLK Rising

20

ns max

DVAL High Delay After RESET Low

3

ns max

Data Access Time After SCLK Falling Edge

ns max

Data Valid Time Before SCLK Rising Edge

NOTES

°C to ensure compliance.

TO

OUTPUT

PIN

50pF

200 A

1.6mA

1.6V

Figure 2. Load Circuit for Access Time and Bus Relinquish Time

SCLK (O)

DATA (O)

NOTE:

O SIGNIFIES AN OUTPUT

Figure 3. Data Timing

MCLK (I)

RESET (I)

DVAL (O)

NOTE:

I SIGNIFIES AN INPUT

O SIGNIFIES AN OUTPUT

Figure 4. RESET Timing

(AVDD = 5 V

5%; DVDD = 5 V

5%; DVDD1 = 3 V

5%; AGND = DGND = 0 V, REF2A =

REF2B = 2.5 V, unless otherwise noted.)