ADP5585ACPZ-00-R7 datasheet(4/40 Pages) AD

4 / 40 page

ADP5585

Data Sheet

Rev. C | Page 4 of 40

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

I2C TIMING SPECIFICATIONS

Delay from UVLO/Reset Inactive to I2C Access

μs

SCL Clock Frequency

fSCL

1000

kHz

SCL High Time

tHIGH

0.26

μs

SCL Low Time

tLOW

0.5

μs

Data Setup Time

tSU; DAT

Data Hold Time

tHD; DAT

μs

Setup Time for Repeated Start

tSU; STA

0.26

μs

Hold Time for Start/Repeated Start

tHD; STA

0.26

μs

Bus Free Time for Stop and Start Condition

tBUF

0.5

μs

Setup Time for Stop Condition

tSU; STO

0.26

μs

Data Valid Time

tVD; DAT

0.45

μs

Data Valid Acknowledge

tVD; ACK

0.45

μs

Rise Time for SCL and SDA

120

Fall Time for SCL and SDA

120

Pulse Width of Suppressed Spike

tSP

Capacitive Load for Each Bus Line

CB4

550

1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Typical values are at TA = 25°C, VDD = 1.8 V.

2 Guaranteed by design.

3 All timers are referenced from the base oscillator and have the same ±10% accuracy.

4 CB is the total capacitance of one bus line in picofarads.

TIMING DIAGRAM

SDA

SCL

SDA

SCL

FIRST CLOCK CYCLE

NINTH CLOCK

fSCL

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

70%

30%

tHIGH

tVD; DAT

tSU; DAT

tSU; STA

tHD; DAT

tHD; STA

tVD; ACK

tSP

tSU; STO

tBUF

tLOW

tHD; STA

VIL = 0.3VDD

VIH = 0.7VDD

Figure 2. I2C Interface Timing Diagram

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