ADP5585ACBZ-01-R7 datasheet(31/40 Pages) AD

31 / 40 page

Data Sheet

ADP5585

Rev. C | Page 31 of 40

RESET1_EVENT_B Register 0x2A

Table 50. RESET1_EVENT_B Bit Descriptions

Bit(s)

Bit Name

Access

Description

RESET1_EVENT_B_LEVEL

Read/write

Defines which level the second reset event should be to generate the RESET1

signal. Refer to Table 49.

6 to 0

RESET1_EVENT_B[6:0]

Read/write

Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.

RESET1_EVENT_C Register 0x2B

Table 51. RESET1_EVENT_C Bit Descriptions

Bit(s)

Bit Name

Access

Description

RESET1_EVENT_C_LEVEL

Read/write

Defines which level the second reset event should be to generate the RESET1

signal. Refer to Table 49.

6 to 0

RESET1_EVENT_C[6:0]

Read/write

Defines an event that can be used to generate the RESET1 signal. Refer to Table 11.

RESET2_EVENT_A Register 0x2C

Table 52. RESET2_EVENT_A Bit Descriptions

Bit(s)

Bit Name

Access

Description

RESET2_EVENT_A_LEVEL

Read/write

Defines which level the first reset event should be to generate the RESET2 signal.

For key events, use the following settings:

0 = not applicable; releases not used for reset generation.

1 = press is used as reset event.

For GPIs and logic outputs configured for FIFO updates, use the following settings:

0 = inactive event used as reset condition.

1 = active event used as reset condition.

6 to 0

RESET2_EVENT_A[6:0]

Read/write

Defines an event that can be used to generate the RESET2 signal. Up to two events

can be defined for generating the RESET2 signal, using RESET2_EVENT_A[6:0], and

RESET2_EVENT_B[6:0]. If one of the registers is 0, that register is not used for reset

generation. All reset events must be detected at the same time to trigger the reset.

RESET2_EVENT_B Register 0x2D

Table 53. RESET2_EVENT_B Bit Descriptions

Bit(s)

Bit Name

Access

Description

RESET2_EVENT_B_LEVEL

Read/write

Defines which level the second reset event should be to generate the RESET2

signal. Refer to Table 52.

6 to 0

RESET2_EVENT_B[6:0]

Read/write

Defines an event that can be used to generate the RESET2 signal. Refer to Table 11.

RESET_CFG Register 0x2E

Table 54. RESET_CFG Bit Descriptions

Bit(s)

Bit Name

Access

Description

RESET2_POL

Read/write

Sets the polarity of RESET2.

0 = RESET2 is active low.

1 = RESET2 is active high.

RESET1_POL

Read/write

Sets the polarity of RESET1.

0 = RESET1 is active low.

1 = RESET1 is active high.

RST_PASSTHRU_EN

Read/write

Allows the RST pin to override (OR with) the RESET1signal. This function not

applicable to RESET2.

ADP5585ACBZ-01-R7 数据表(PDF) 31 Page - Analog Devices

ADP5585ACBZ-01-R7 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表下载

链接网址

ADP5585ACBZ-01-R7 数据表(PDF) 31 Page - Analog Devices

ADP5585ACBZ-01-R7 数据表(HTML) 31 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

数据表 下载

链接网址

数据表下载