AD7708 datasheet(22/44 Pages) AD

22 / 44 page

REV. 0

–22–

AD7708/AD7718

ON-CHIP REGISTERS

The AD7708 and AD7718 are controlled and configured via

a number of on-chip registers which are shown in Figure 15.

The first of these registers is the communications register

which is used to control all operations on these converters. All

communications with these parts must start with a write to

the communications register to specify the next operation to

be performed. After a power-on or RESET, the device defaults

to waiting for a write to the communications register. The

STATUS register contains information pertaining to the operat-

ing conditions of the converter. The STATUS register is a read

only register. The MODE register is used to configure the con-

version mode, calibration, chop enable/disable, reference select,

channel configuration and buffered or unbuffered operation on

the AINCOM analog input. The MODE register is a read/write

to select the active channel and program its input range and

bipolar/unipolar operation. The I/O control register is a read/

write register used to configure the operation of the 2-pin I/O

port. The filter register is a read/write register used to program

the data update rate of the converter. The ADC Data register is

a read only register that contains the result of a data conversion

on the selected channel. The ADC offset registers are read/write

registers that contain the offset calibration data. There are five

offset registers, one for each of the fully differential input channels.

When configured for pseudo-differential input mode the chan-

nels share offset registers. The ADC gain registers are read/write

registers that contain the gain calibration data. There are five

ADC gain registers, one for each of the fully differential input

channels. When configured for pseudo differential input mode

the channels share gain registers. The ADC contains Test registers

for factory use only, the user is advised not to alter the oper-

ating conditions of these registers. The ID register is a read only

ing sections contains more in-depth detail on all of these registers.

In the following descriptions, SET implies a Logic 1 state and

CLEARED implies a Logic 0 state unless otherwise stated.

DOUT

DIN

DOUT

DIN

DOUT

DIN

DOUT

DIN

DOUT

DIN

DOUT

WEN R/W

COMMUNICATIONS REGISTER

DOUT

DIN

SELECT

DECODER

ADC DATA REGISTER

STATUS REGISTER

MODE REGISTER

ADC CONTROL REGISTER

I/O CONTROL REGISTER

FILTER REGISTER

ID REGISTER

TEST REGISTER

ADC GAIN REGISTER

ADC OFFSET REGISTER

DIN

Figure 15. On-Chip Registers

AD7708 数据表(PDF) 22 Page - Analog Devices

AD7708 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载

链接网址

AD7708 数据表(PDF) 22 Page - Analog Devices

AD7708 数据表(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表 下载

链接网址

数据表下载