AD8021 datasheet(13/28 Pages) AD

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AD7986

Rev. B | Page 13 of 28

THEORY OF OPERATION

COMP

CONTROL

LOGIC

SWITCHES CONTROL

BUSY

OUTPUT CODE

CNV

65,536C

131,072C

LSB

SW+

MSB

LSB

SW–

MSB

65,536C

131,072C

IN+

REF

REFGND

IN–

Figure 21. ADC Simplified Schematic

CIRCUIT INFORMATION

The AD7986 is a fast, low power, single-supply, precise, 18-bit

ADC using a successive approximation architecture. The AD7986

features different modes to optimize performance according to

the application. In turbo mode, the AD7986 is capable of convert-

ing 2,000,000 samples per second (2 MSPS).

The AD7986 provides the user with an on-chip track-and-hold

and does not exhibit any pipeline delay or latency, making it ideal

for multiple multiplexed channel applications.

The AD7986 can be interfaced to any 1.8 V to 2.7 V digital logic

family. It is available in a 20-lead LFCSP (QFN) that allows space

savings and flexible configurations.

CONVERTER OPERATION

The AD7986 is a successive approximation ADC based on a

charge redistribution DAC. Figure 21 shows the simplified

schematic of the ADC. The capacitive DAC consists of two

identical arrays of 18 binary-weighted capacitors that are

connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the

input of the comparator are connected to AGND via SW+ and

SW−. All independent switches are connected to the analog

inputs. Therefore, the capacitor arrays are used as sampling

capacitors and acquire the analog signal on the IN+ and IN−

inputs. When the acquisition phase is complete and the CNV

input goes high, a conversion phase is initiated. When the

conversion phase begins, SW+ and SW− are opened first. The

two capacitor arrays are then disconnected from the analog

inputs and connected to the REFGND input. Therefore, the

differential voltage between Input IN+ and Input IN− captured

at the end of the acquisition phase is applied to the comparator

inputs, causing the comparator to become unbalanced. By

switching each element of the capacitor array between

REFGND and REF, the comparator input varies by binary-

weighted voltage steps (VREF/2, VREF/4 … VREF/262,144). The

control logic toggles these switches, starting with the MSB, to

bring the comparator back into a balanced condition. After the

completion of this process, the part returns to the acquisition

phase, and the control logic generates the ADC output code and

a busy signal indicator.

Because the AD7986 has an on-board conversion clock, the

serial clock, SCK, is not required for the conversion process.

CONVERSION MODES OF OPERATION

The AD7986 features two conversion modes of operation: turbo

and normal. Turbo conversion mode (TURBO = high) allows

the fastest conversion rate of up to 2 MSPS, and does not power

down between conversions. The first conversion in turbo mode

should be ignored because it contains meaningless data. For

applications that require lower power and slightly slower

sampling rates, the normal mode (TURBO = low) allows a

maximum conversion rate of 1.5 MSPS, and powers down

between conversion. The first conversion in normal mode does

contain meaningful data.

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