LP3987

SNVS164G – OCTOBER 2001 – REVISED MAY 2013

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Block Diagram

Figure 1. LP3987

Connection Diagram

Figure 2. Top View

5 I/O DSBGA Package

See Package Number YZR0005ADA

PIN DESCRIPTIONS

Name

Function

A1

Enable Input Logic, Enable High

GND

B2

Common Ground

C1

Output voltage of the LDO

C3

Input voltage of the LDO

MODE

A3

Power Mode Control, Active = 1, Sleep Mode = 0

(1)

The pin numbering scheme for the DSBGA package was revised in April, 2002 to conform to JEDEC standard. Only the pin numbers

were revised. No changes to the physical location of the inputs/outputs were made. For reference purposes, the obsolete numbering

scheme had VEN as pin 1, GND as pin 2, VOUT as pin 3, VIN as pin 4, and MODE as pin 5.

2

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