MCP4441 datasheet(74/100 Pages) MICROCHIP

74 / 100 page

MCP444X/446X

DS22265A-page 74

8.2

Using Shutdown Modes

Figure 8-3 shows a possible application circuit where

the

independent

terminals

could

used.

Disconnecting the wiper allows the transistor input to

be taken to the Bias voltage level (disconnecting A and

or B may be desired to reduce system current).

Disconnecting Terminal A modifies the transistor input

by the RBW rheostat value to the Common B.

Disconnecting Terminal B modifies the transistor input

by the RAW rheostat value to the Common A. The

Common A and Common B connections could be

connected to VDD and VSS.

FIGURE 8-3:

Example Application Circuit

using Terminal Disconnects.

8.3

Software Reset Sequence

At times, it may become necessary to perform a

Software Reset Sequence to ensure the MCP44XX

device is in a correct and known I2C Interface state.

This technique only resets the I2C state machine.

This is useful if the MCP44XX device powers up in an

incorrect state (due to excessive bus noise, etc), or if

the Master Device is reset during communication.

Figure 8-4 shows the communication sequence to

software reset the device.

FIGURE 8-4:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device. In this mode, the device is monitoring

the data bus in Receive mode and can detect the Start

bit forces an internal Reset.

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP44XX is driving an A bit on

the I2C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I2C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP44XX holding the bus

low. By sending out nine ‘1’ bits, it is ensured that the

device will see a A bit (the Master Device does not drive

the I2C bus low to acknowledge the data sent by the

MCP44XX), which also forces the MCP44XX to reset.

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP44XX, AND then as the Master Device returns

to normal operation and issues a Start condition while

the MCP44XX is issuing an Acknowledge. In this case,

if the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP44XX could initiate a write cycle.

The Stop bit terminates the current I2C bus activity. The

MCP44XX waits to detect the next Start condition.

This sequence does not effect any other I2C devices

which may be on the bus, as they should disregard this

as an invalid command.

Balance

Bias

Input

To base

of Transistor

(or Amplifier)

Common B

Common A

Note:

This technique is documented in AN1028.

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP44XX.

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

Start

bit

Nine bits of ‘1’

Start bit

Stop bit

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