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DSPIC30F2011AT-30E/PF 数据表(PDF) 13 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF 数据表(HTML) 13 Page - Microchip Technology |
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13 / 238 page  © 2006 Microchip Technology Inc. Preliminary DS70143C-page 11 dsPIC30F6011A/6012A/6013A/6014A FIGURE 1-2: dsPIC30F6013A/6014A BLOCK DIAGRAM AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 Power-up Timer Oscillator Start-up Timer POR/BOR Reset Watchdog Timer Instruction Decode & Control OSC1/CLKI MCLR VDD, VSS AN4/CN6/RB4 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 Low-Voltage Detect UART1, INT4/RA15 INT3/RA14 VREF+/RA10 VREF-/RA9 CAN2 Timing Generation CAN1, AN5/CN7/RB5 16 PCH PCL Program Counter ALU<16> 16 24 24 24 24 X Data Bus IR I2C™ DCI AN6/OCFA/RB6 AN7/RB7 PCU 12-bit ADC Timers SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 SS2/CN11/RG9 U2TX/CN18/RF5 EMUC3/SCK1/INT0/RF6 SDI1/RF7 EMUD3/SDO1/RF8 Input Capture Module Output Compare Module EMUC1/SOSCO/T1CK/CN0/RC14 EMUD1/SOSCI/CN1/RC13 T4CK/RC3 T2CK/RC1 PORTB C1RX/RF0 C1TX/RF1 U1RX/RF2 U1TX/RF3 C2RX/RG0 C2TX/RG1 SCL/RG2 SDA/RG3 PORTG PORTD 16 16 16 16 x 16 W Reg Array Divide Unit Engine DSP Decode ROM Latch 16 Y Data Bus Effective Address X RAGU X WAGU Y AGU PGD/EMUD/AN0/CN2/RB0 PGC/EMUC/AN1/CN3/RB1 AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC2/CLKO/RC15 U2RX/CN17/RF4 AVDD, AVSS UART2 SPI2 16 16 16 16 16 PORTA PORTC PORTF 16 16 16 16 8 Interrupt Controller PSV & Table Data Access Control Block Stack Control Logic Loop Control Logic Data Latch Data Latch Y Data RAM X Data RAM Address Latch Address Latch Control Signals to Various Blocks EMUC2/OC1/RD0 EMUD2/OC2/RD1 OC3/RD2 OC4/RD3 OC5/CN13/RD4 OC6/CN14/RD5 OC7/CN15/RD6 OC8/CN16/RD7 IC1/RD8 IC2/RD9 IC3/RD10 IC4/RD11 IC5/RD12 IC6/CN19/RD13 IC7/CN20/RD14 IC8/CN21/RD15 16 *CSDI/RG12 *CSDO/RG13 *CSCK/RG14 *COFS/RG15 T3CK/RC2 SPI1, INT1/RA12 INT2/RA13 CN23/RA7 CN22/RA6 T5CK/RC4 Address Latch Program Memory (Up to 144 Kbytes) Data Latch Data EEPROM (Up to 4 Kbytes) 16 * CSDI, CSDO, CSCK, and COFS are codec functions on dsPIC30F6014A only |
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