DM163006 datasheet(83/320 Pages) MICROCHIP

83 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 83

PIC18C601/801

6.4

Long Writes

Long writes will not be supported on the PIC18C601/801

to program FLASH configuration memory. The configu-

ration locations can only be programmed in ICSP mode.

6.5

External Wait Cycles

The Table Reads and Writes have the capability to

insert wait states when accessing external memory.

These wait states only apply to the execution of a Table

Read or Write to external memory and not to instruction

fetches out of external memory. The guidelines pre-

sented in Section 5.0 must be followed to select the

proper memory speed grade for the device operating

frequency.

The WAIT<1:0> bits in the MEMCON register will select

0, 1, 2, or 3 extra TCY cycles per TBLRD/TBWLT cycle.

The wait will occur on Q4.

The default setting of the wait on power-up is to assert

a maximum wait of 3TCY cycles. This insures that slow

memories will work in Microprocessor mode immedi-

ately after RESET.

Figure 6-11 shows 8-bit external bus timing for a Table

Read with 2 wait cycles. Figure 6-12 shows 16-bit

external bus timing for a Table Read with 1 wait cycle.

FIGURE 6-11:

EXTERNAL INTERFACE TIMING (8-BIT MODE)

A<19:8>

ALE

ABh

AD<7:0>

CCFh

BA0

33h

Opcode Fetch

MOVLW 55h

03Ah

55h

92h

from 007556h

2TCY Wait

0Eh

Table Read

of 92h

from 199E67h

Apparent Q

Actual Q

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