17

®

PCM1750

USING AN EXTERNAL REFERENCE

Typical Performance Curves. If better drift or power supply

rejection performance is desired, one of the external refer-

ence circuits shown in Figures 8b and 8c can be used. Note

External gain adjustment is now possible by using the

variable output options available on some precision voltage

references or by varying the gain on external buffer ampli-

fiers. The range of acceptable external references is from

commonly available. Full scale input voltage range will be

±VREF

If an external reference is used, P19 and P24 must be

bypassed with at least 1

µF capacitors.

SAMPLING A/D SYSTEM

Figure 9 is a partial schematic of the demonstration fixture

for the PCM1750 (orderable by model number DEM1133).

It shows the implementation of (1) a 6th order, linear-phase,

anti-aliasing filter (22kHz low-pass); (2) the PCM1750P

A/D converter; and (3) a 4x digital decimation filter called

the DF1750P. Not shown on this schematic, but included on

the demo fixture, are latched parallel data outputs with

strobe and a serial digital interface format (SPDIF) data

transmitter. Also included on the DEM1133 are user bread-

board areas for application specific circuit implementation.

CONNECTION TO DSP WITH DIGITAL FILTER

The PCM1750 and DF1750 combination can be connected to

the serial ports of most popular DSP processor ICs (such as

those made by AT&T, Motorola, TI, and AD) by adding a

small amount of external glue logic. Figures 10 and 11 show

the timing diagram and schematic for this interface.

To use this interface, the DSP processor IC must be configured

for 32-bit word inputs. The glue logic generates a flag bit, as

the first bit of the 32-bit word, that signifies either left or right

channel data. The flag bit will be low for left channel data and

high for right channel data.

The DF1750 can be configured for either 16- or 20-bit data,

although only 16-bit data is shown in Figure 10. After the data

is transferred into the DSP processor IC, it must be shifted

toward the LSB by one bit in order to compensate for a clock

delay in the glue logic.

FIGURE 10. PCM1750/DF1750 To DSP IC Timing Diagram.

LRCK

(LRPOL = H)

WDCK

Frame Syn L

Flag Enable

Bit Clock

Data to DSP

DATA

DATA

Channel Flag (Right Channel)