LP3906

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SNVS456M – AUGUST 2006 – REVISED MAY 2013

SHUTDOWN MODE

During shutdown the PFET switch, reference, control and bias circuitry of the converters are turned off. The

NFET switch will be on in shutdown to discharge the output. When the converter is enabled, soft start is

activated. It is recommended to disable the converter during the system power up and under voltage conditions

when the supply is less than 2.8V.

SOFT START

The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thus

reducing start-up stresses and surges. The two LP3906 buck converters have a soft-start circuit that limits in-

rush current during start-up. During start-up the switch current limit is increased in steps. Soft start is activated

only if EN goes from logic low to logic high after VIN reaches 2.8V. Soft start is implemented by increasing switch

current limit in steps of 213 mA, 425 mA, 850 mA and 1700 mA (typ. Switch current limit). The start-up time

thereby depends on the output capacitor and load current demanded at start-up.

LOW DROPOUT OPERATION

The LP3906 can operate at 100% duty cycle (noswitching; PMOS switch completely on) for low drop out support

of the output voltage. In this way the output voltage will be controlled down to the lowest possible input voltage.

When the device operates near 100% duty cycle, output voltage ripple is approximately 25 mV. The minimum

input voltage needed to support the output voltage is:

Where:

Load current

Drain to source resistance of

PFET switch in the triode region

Inductor resistance

FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER SUPPLIES

The LP3906 provides several options for power on sequencing. The two bucks can be individually controlled with

ENSW1 and ENSW2. The two LDOs can also be individually controlled with ENLDO1 and ENLDO2.

If the user desires a set power on sequence, all four enables should be tied LOW so that the regulators don’t

from LOW to HIGH to activate the power on sequencing.

POWER ON

EN_T assertion causes the LP3906 to emerge from Standby mode to Full Operation mode at a preset timing

sequence. By default, the enables for the LDOs and Bucks are internally pulled up, which causes the part to turn

ON automatically. If the user wishes to have a preset timing sequence to power on the regulators, the external

regulator enables must be tied LOW. Otherwise, simply tie the enables of each specific regulator HIGH.

EN_T is edge triggered with rising edge signaling the chip to power on. The EN_T input is deglitched and the

default is set at 1 ms. As shown in the next 2 diagrams, a rising EN_T edge will start a power on sequence, while

a falling EN_T edge will start a shutdown sequence. If EN_T is high, toggling the external enables of the

regulators will have no effect on the chip.

Table 3. Default Power ON Sequence:

1.5

2.0

3

6

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