L7980 datasheet(22/44 Pages) STMICROELECTRONICS

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Application informations

L7980

22/44

Doc ID 15181 Rev 4

Equation 21

where K is the feed forward constant and 1/K is equals to 9.

Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):

Equation 22

Calculate C5 by placing the second pole at four times the system bandwidth (BW):

Equation 23

Set also the first pole at four times the system bandwidth and also the second zero at

the output filter double pole:

Equation 24

The suggested maximum system bandwidth is equals to the switching frequency divided by

3.5 (FSW/3.5), anyway lower than 100 kHz if the FSW is set higher than 500 kHz.

For example with VOUT=5 V, VIN=24 V, IO=2 A, L=27 μH, COUT=22 μF, ESR<1 mΩ, the type

III compensation network is:

In Figure 12 is shown the module and phase of the open loop gain. The bandwidth is about

54 kHz and the phase margin is 50°.

---------- KR

⋅⋅

π R

⋅⋅

---------------------------

π R

4BW

⋅

–

⋅⋅⋅

--------------------------------------------------------------

4BW

⋅

-----------------

–

---------------------------

π R

4BW

⋅⋅ ⋅

-----------------------------------------

4.99k

680

150

3.3k

4.7nF

22nF

220pF

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