L7980ATR datasheet(25/44 Pages) STMICROELECTRONICS

25 / 44 page

L7980

Application informations

Doc ID 15181 Rev 4

25/44

Figure 14.

Open loop gain: module bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follow:

Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4

and C5 not comparable with parasitic capacitance of the board.

Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 25

Where fESR is the ESR zero:

Equation 26

and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant.

Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 27

Then calculate C3 in order to place the second pole at four times the system bandwidth

(BW):

ESR

------------

⎝⎠

⎛⎞

ESR

------------

--------- R

⋅⋅

⋅

ESR

π ESR C

OUT

⋅⋅

--------------------------------------------

π R

⋅⋅

-------------------------------

L7980ATR 数据表(PDF) 25 Page - STMicroelectronics

L7980ATR 数据表(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

数据表下载