5CSXC5 datasheet(21/74 Pages) ALTERA

21 / 74 page

Chapter 1: Overview for Cyclone V Device Family

1–15

Dynamic and Partial Reconfiguration

February 2012

Altera Corporation

Cyclone V Device Handbook

Volume 1: Device Overview and Datasheet

Table 1–13 lists the supported memory configurations for Cyclone V devices.

Dynamic and Partial Reconfiguration

The dynamic reconfiguration feature allows you to dynamically change the

transceiver data rates, PMA settings, or protocols of a channel, without affecting data

transfer on adjacent channels. This feature is ideal for applications that require

on-the-fly multiprotocol or multirate support. You can reconfigure the PMA and PCS

blocks with dynamic reconfiguration.

Partial reconfiguration allows you to reconfigure part of the device while other

sections of the device remain operational. This capability is important in systems with

critical uptime requirements because it allows you to make updates or adjust

functionality without disrupting services.

Apart from lowering cost and power consumption, partial reconfiguration increases

the effective logic density of the device because placing device functions that do not

operate simultaneously is not necessary. Instead, you can store these functions in

external memory and load them whenever the functions are required. This capability

reduces the size of the device because it allows multiple applications on a single

device—saving the board space and reducing the power consumption.

Altera simplifies the time-intensive task of partial reconfiguration by building this

capability on top of the proven incremental compile and design flow in the Quartus II

design software. With the Altera® solution, you do not need to know all the intricate

device architecture details to perform a partial reconfiguration.

Partial reconfiguration is supported through the FPP x16 configuration interface. You

can seamlessly use partial reconfiguration in tandem with dynamic reconfiguration to

enable simultaneous partial reconfiguration of both the device core and transceivers.

Clock Networks and PLL Clock Sources

The Cyclone V clock network architecture is based on Altera’s proven global,

quadrant, and peripheral clock structure, which is supported by dedicated clock input

pins and fractional PLLs. Cyclone V devices have 16 global clock networks capable of

up to 550 MHz operation. The Quartus II software identifies all unused sections of the

clock network and powers them down, which reduces power consumption.

Table 1–13. Embedded Memory Block Configurations for Cyclone V Devices

Memory Block

Depth (bits)

Programmable Widths

MLAB

x1, x2, x4, x8, x9, x10, x16, x18, or x20

M10K

256

x40 or x32

512

x20 or x16

x10 or x8

x5 or x4

5CSXC5 数据表(PDF) 21 Page - Altera Corporation

5CSXC5 数据表(HTML) 21 Page - Altera Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

数据表下载