ThunderLAN

™ TNETE100A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T WITH MII FOR 100 BASE-T/100VG-AnyLAN

SPWS021B – OCTOBER 1995 – REVISED NOVEMBER 1996

15

POST OFFICE BOX 1443

AUI receiver input (ARCVP, ARCVN, ACOLP, ACOLN)

PARAMETER

JEDEC

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

VI(DIFF)1

Differential input voltage 1†

VID(1)

See Note 12

0

3

V

VI(DIFF)2

Differential input voltage 2†

VID(2)

See Note 13

0

100

mV

V(SQ–)

Falling input pair squelch threshold

– 325

mV

† Refer to recommended operating conditions

NOTES: 12. Common-mode frequency range : 0 Hz to 40 kHz

13. Common-mode frequency range : 40 kHz to 10 MHz

AUI transmitter drive characteristics (AXMTP, AXMTN)

PARAMETER

JEDEC

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

VO(DIFF)1

Differential output voltage‡

VOD(1)

See Note 14

"240 "1300

mV

VOI(DIFF)

Output idle differential voltage†

VOD(IDLE)

"50

mV

VOI(DIFF)U

Output differential undershoot†§

VOD(IDLE)U

100

mV

IO(FC)

Output current, fault condition‡

IO(FC)

150

mA

† Refer to recommended operating conditions

‡ Specified by design

§ Characterized but not tested

NOTE 14: The differential voltage is measured as per Figure 3b.

crystal oscillator characteristics

PARAMETER

JEDEC

SYMBOL

TEST CONDITIONS

MIN

MAX

UNIT

VSB(FXTL1) Input self-bias voltage

VIB

1.7

2.8

V

IOH(FXTL2)

High-level output current (see Note 4)

IOH

V(FXTL2) = VSB(FXTL1)

V(FXTL1) = VSB(FXTL1) + 0.5 V

– 1.3

– 5.0

mA

IOL(FXTL2)

Low-level output current

IOL

V(FXTL2) = VSB(FXTL1)

V(FXTL1) = VSB(FXTL1) – 0.5 V

0.4

1.5

mA

NOTE 4: The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels only.

PARAMETER MEASUREMENT INFORMATION

Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels

are compatible with TTL devices.

Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,

the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low

is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level

at which the signal is said to be high is 2 V, as shown below.

The rise and fall times are not specified but are assumed to be those of standard TTL devices, which are typically

1.5 ns.

0.8 V (low)

2 V (high)