8

LT1072

1072fc

rough guide to calculate LT1072 power dissipation. For

more details, the reader is referred to Application Note 19

(AN19), “Efficiency Calculations” section.

Average supply current (including driver current) is:

DC = switch duty cycle

Switch power dissipation is given by:

Total power dissipation is the sum of supply current times

input voltage plus switch power:

In a typical example, using a boost converter to generate

12V @ 0.12A from a 5V input, duty cycle is approximately

60%, and switch current is about 0.65A, yielding:

Temperature rise in a plastic miniDIP would be 130°C/W

times 0.34W, or approximately 44°C. The maximum

ambient temperature would be limited to 100°C

(commercial temperature limit) minus 44°C, or 56°C.

In most applications, full load current is used to calculate

die temperature. However, if overload conditions must

also be accounted for, four approaches are possible. First,

if loss of regulated output is acceptable under overload

conditions, the internal

thermal limit of the LT1072 will

protect the die in most applications by shutting off switch

current.

Thermal limit is not a tested parameter, however,

and should be considered only for non-critical applications

with temporary overloads. A second approach is to use the

larger TO-220 (T) or TO-3 (K) package which, even without

a heat sink, may limit die temperatures to safe levels under

overload conditions. In critical situations, heat sinking

of these packages is required; especially if overload

conditions must be tolerated for extended periods of time.

The third approach for lower current applications is to

leave the second switch emitter open. This increases

switch “on” resistance by 2:1, but reduces switch current

switch dissipation under current limit conditions.

than its internal clamp level of 2V. The LT1072 switch

externally clamped between these two levels with a diode.

See AN-19 for details.

LT1072 Synchronizing

The LT1072 can be externally synchronized in the frequency

range of 48kHz to 70kHz. This is accomplished as shown

in the accompanying figures. Synchronizing occurs when

To avoid disturbing the DC characteristics of the internal

error amplifier, the width of the synchronizing pulse

should be under 1µs. C2 sets the pulse width at ≈ 0.35µs.

The effect of a synchronizing pulse on the LT1072

amplifier offset can be calculated from:

KT

= 26mV at 25°C

q

R3 = resistor used to set mid-frequency “zero” in LT1072

frequency compensation network.

offset voltage shift is ≈2.2mV. This is not particularly

bothersome, but note that high offsets could result

if R3 were reduced to a much lower value. Also, the

synchronizing transistor must sink higher currents with

low values of R3, so larger drives may have to be used. The

200mV of ground to ensure synchronizing.

LT1072 OPERATIO

KT

q

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