PCF8536AT datasheet(14/74 Pages) NXP

14 / 74 page

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

14 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

[1]

When RESET is active, the internal oscillator is off.

[2]

Special case. The PWM generator needs 230 kHz and must be enabled when PWM is enabled.

It is possible to make the internal oscillator signal available on pin OSCCLK by using the

oscillator-control command (see Table 10) and configuring the clock output enable (COE)

bit. If not required, the pin OSCCLK should be left open or connected to VSS. At power-on

the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state.

Clock output is only valid when using the internal oscillator. The signal will appear on the

OSCCLK pin.

An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this

clock varies with the chosen divide ratio.

[1]

When RESET is active, the pin OSCCLK is in 3-state.

[2]

In this state, an external clock may be applied, but it is not a requirement.

[3]

9.6 kHz is the nominal frequency with q = 24, see Table 15.

External clock: In applications where an external clock must be applied to the PCF8536,

bit OSC (see Table 10) has to be set logic 1. In this case pin OSCCLK becomes an input.

The OSCCLK signal must switch between the VSS and the VDD voltage supplied to the

chip.

The system is designed for a 230 kHz clock or alternatively for using a 9.6 kHz clock. The

EFR bit determines the external clock frequency. The clock frequency (fclk(ext)) in turn

determines the LCD frame frequency, see Table 15.

The PWM generator requires a 230 kHz clock to operate. If PWM is enabled and an

external clock of 9.6 kHz is selected, then the internal oscillator will automatically start and

be used for the PWM signal generation.

Table 13.

Internal oscillator on/off table

OSC

PWM

EFR

Internal

oscillator state[1]

power-down

n.a.

off

power-up

internal oscillator

n.a.

external oscillator

off

n.a.

off

9.6 kHz

on[2]

230 kHz

off

Table 14.

OSCCLK table

OSC

COE

EFR

OSCCLK pin[1]

power-down

n.a.

off

n.a.

3-state[2]

power-down

n.a.on

n.a.VDD

power-up

internal oscillator

off

n.a.

3-state

n.a.

9.6 kHz output[3]

external oscillator

n.a.

9.6 kHz

9.6 kHz input

230 kHz

230 kHz input

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