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MPC8548ECPXAVJB 数据表(PDF) 10 Page - Freescale Semiconductor, Inc

部件名 MPC8548ECPXAVJB
功能描述  Integrated Processor Hardware Specifications
PDF  151 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC8548ECPXAVJB 数据表(HTML) 10 Page - Freescale Semiconductor, Inc

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
10
Freescale Semiconductor
Electrical Characteristics
2
Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the device.
This device is currently targeted to these specifications. Some of these specifications are independent of
the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design
specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
The following table provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
VDD
–0.3 to 1.21
V
—
PLL supply voltage
AVDD
–0.3 to 1.21
V
—
Core power supply for SerDes transceivers
SVDD
–0.3 to 1.21
V
—
Pad power supply for SerDes transceivers
XVDD
–0.3 to 1.21
V
—
DDR and DDR2 DRAM I/O voltage
GVDD
–0.3 to 2.75
–0.3 to 1.98
V
2
Three-speed Ethernet I/O voltage
LVDD (for eTSEC1
and eTSEC2)
–0.3 to 3.63
–0.3 to 2.75
V
TVDD (for eTSEC3
and eTSEC4)
–0.3 to 3.63
–0.3 to 2.75
3
PCI/PCI-X, DUART, system control and power management,
I2C, Ethernet MII management, and JTAG I/O voltage
OVDD
–0.3 to 3.63
V
—
Local bus I/O voltage
BVDD
–0.3 to 3.63
–0.3 to 2.75
V—
Input voltage
DDR/DDR2 DRAM signals
MVIN
–0.3 to (GVDD + 0.3)
V
4
DDR/DDR2 DRAM reference
MVREF
–0.3 to
(GVDD/2 + 0.3)
V—
Three-speed Ethernet I/O signals
LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V
4
Local bus signals
BVIN
–0.3 to (BVDD + 0.3)
—
—
DUART, SYSCLK, system control and power
management, I2C, Ethernet MII management,
and JTAG signals
OVIN
–0.3 to (OVDD + 0.3)
V
4
PCI/PCI-X
OVIN
–0.3 to (OVDD + 0.3)
V
4



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