ADA4891-1/ADA4891-2

Rev. A | Page 16 of 20

LAYOUT, GROUNDING, AND BYPASSING

POWER SUPPLY BYPASSING

Power supply pins are additional op amp inputs, and care must be

taken so that a noise-free stable dc voltage is applied. The purpose

of bypass capacitors is to create a low impedance path from the

supply to ground over a range of frequencies, thereby shunting

or filtering the majority of the noise to ground. Bypassing is

also critical for stability, frequency response, distortion, and PSRR

performance.

Chip capacitors of 0.1 μF (X7R or NPO) are critical and should

be as close as possible to the amplifier package. The 0508 case

size for such a capacitor is recommended because it offers low

series inductance and excellent high frequency performance.

Larger chip capacitors, such as 0.1 μF capacitors, can be shared

among a few closely spaced active components in the same

signal path. A 10 μF tantalum capacitor is less critical for high

frequency bypassing, but does provide additional bypassing for

lower frequencies.

GROUNDING

When possible, ground and power planes should be used. Ground

and power planes reduce the resistance and inductance of the

power supply feeds and ground returns. If multiple planes are

used, they should be stitched together with multiple vias. The

returns for the input, output terminations, bypass capacitors,

Ground vias should be placed at the very end of the component

mounting pads to provide a solid ground return. The output load

ground and the bypass capacitor grounds should be returned

to a common point on the ground plane to minimize parasitic

inductance that can help improve distortion performance.

INPUT AND OUTPUT CAPACITANCE

Parasitic capacitance can cause peaking and instability and,

therefore, should be minimized to ensure stable operation.

High speed amplifiers are sensitive to parasitic capacitance between

the inputs and ground. A few picofarads of capacitance reduces

the input impedance at high frequencies, in turn increasing the

gain of the amplifier and causing peaking of the frequency

response or even oscillations, if severe enough. It is recommended

that the external passive components, which are connected to

the input pins, be placed as close as possible to the inputs to

avoid parasitic capacitance.

In addition, all ground and power planes under the pins of

the ADA4891 should be cleared of copper to prevent parasitic

capacitance between the input and output pins to ground. This is

because a single mounting pad on a SOIC footprint can add as

much as 0.2 pF of capacitance to ground if the ground or power

plane is not cleared under the ADA4891 pins. In fact, the ground

and power planes should be kept at a distance of at least 0.05 mm

from the input pins on all layers of the board.

INPUT-TO-OUTPUT COUPLING

To minimize capacitive coupling between the inputs and output

and to avoid any positive feedback, the input and output signal

traces should not be parallel. In addition, the input traces should

not be close to each other. A minimum of 7 mils between the

two inputs is recommended.

LEAKAGE CURRENTS

In extremely low input bias current amplifier applications, stray

leakage current paths must be kept to a minimum. Any voltage

differential between the amplifier inputs and nearby traces sets

up a leakage path through the PCB. Consider a 1 V signal and

100 GΩ to ground present at the input of the amplifier. The

resultant leakage current is 10 pA; this is 5× the typical input

bias current of the amplifier. Poor PCB layout, contamination,

and the board material can create large leakage currents. Common

contaminants on boards are skin oils, moisture, solder flux, and

cleaning agents. Therefore, it is imperative that the board be

thoroughly cleaned and the board surface be free of contaminants

to take full advantage of the low input bias currents of the ADA4891.

To significantly reduce leakage paths, a guard-ring/shield should be

used around the inputs. The guard-ring circles the input pins

and is driven to the same potential as the input signal, thereby

reducing the potential difference between pins. For the guard

ring to be completely effective, it must be driven by a relatively

low impedance source and should completely surround the

input leads on all sides, above, and below, using a multilayer

board (see Figure 53). The SOT-23-5 package presents a challenge

in keeping the leakage paths to a minimum. The pin spacing is

very tight, so extra care must be used when constructing the guard

ring (see Figure 54 for recommended guard-ring construction).

NONINVERTING

GUARD RING

INVERTING

GUARD RING

Figure 53. Guard-Ring Configurations

+V

–IN

+IN

–V

+V

–IN

+IN

–V

ADA4891

ADA4891

NONINVERTING

INVERTING

Figure 54. Guard-Ring Layout SOT-23-5