ADP5037ACPZ-R7 datasheet(18/28 Pages) AD

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ADP5037

Data Sheet

Rev. D | Page 18 of 28

100% Duty Operation

With a drop in input voltage, or with an increase in load current,

the buck may reach a limit where, even with the pFET switch

on 100% of the time, the output voltage drops below the desired

output voltage. At this limit, the buck transitions to a mode where

the pFET switch stays on 100% of the time. When the input

conditions change again and the required duty cycle falls, the

buck immediately restarts PWM regulation without allowing

overshoot on the output voltage.

Active Pull-Downs

All regulators have optional, factory programmable, active pull-

down resistors discharging the respective output capacitors

when the regulators are disabled. The pull-down resistors are

connected between VOUTx and AGND. Active pull-downs are

disabled when the regulators are turned on. The typical value of

the pull-down resistor is 600 Ω for the LDOs and 75 Ω for the

bucks. Figure 46 shows the activation timings for the active

pull-downs during regulator activation and deactivation.

LDO1 AND LDO2

The ADP5037 contains two LDOs with low quiescent current

and low dropout voltage, and provides up to 300 mA of output

current. Drawing a low 10 μA quiescent current (typical) at no load

makes the LDO ideal for battery-operated portable equipment.

Each LDO operates with an input voltage of 1.7 V to 5.5 V. The

wide operating range makes these LDOs suitable for cascading

configurations where the LDO supply voltage is provided from

one of the buck regulators.

Each LDO output voltage is set through external resistor dividers

as shown in Figure 48 for LDO1. The output voltage can optionally

be factory programmed to default values as indicated in the

Ordering Guide section. In this event, Ra and Rb are not needed,

and FB3 must be connected to the top of the capacitor on

VOUT3. FB3 is 0.5 V.

LDO1

FB3

VOUT3

VIN3

1µF

VOUT3 = VFB3

+ 1

Figure 48. LDO1 External Output Voltage Setting

The LDOs also provide high power supply rejection ratio (PSRR),

low output noise, and excellent line and load transient response

with only a small 1 µF ceramic input and output capacitor.

LDO1 is optimized to supply analog circuits because it offers

better noise performance compared to LDO2. LDO1 should be

used in applications where noise performance is critical.

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